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IEEE Transactions on Applied Superconductivity

A High-Throughput Multiply-Accumulate Unit With Long Feedback Loop Using Low-Voltage Rapid Single-Flux Quantum Circuits

Ikki Nagaoka, Ryota Kashima, Koki Ishida, Masamitsu Tanaka, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki

Published Jan 30, 2023• 2 citations
Publisher

Abstract

In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm$\boldsymbol{^{2}}$Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.

DOI
10.1109/tasc.2023.3239329

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In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm2\boldsymbol{^{2}}2Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.
A high-throughput 4$\boldsymbol{\times }4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm\boldsymbol{^2},Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134, Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134,Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134\boldsymbol{\mu }W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40W, respectively. Although the switching speed of the Josephson junctions was reduced by 40W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40\boldsymbol{\%}$owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.
We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.
We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm2^22Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm × 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.
In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased; thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz operation. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm2^{2}2process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.