Abstract This paper presents the equipment and programming design that can be utilized in these frameworks which carries out pragmatic quantum key conveyance (QKD) and quantum arbitrary number age (QRNG). Plans This engineering makes the most of the capacities of the framework on a chip (SoC) that executes Programmable door cluster (FPGA) and double center CPU. Relegating time-bound errands For FPGA and CPU the executives, we have made an adaptable framework with ideal asset designation. A business off-the-rack (COTS) assessment board that incorporates the SoC. Likewise with a change For information stream, the general framework design can be utilized as QKD transmitter, QKD collector. what's more, the control and acknowledgment unit QRNG. At last, we utilized double center execution and saw the synchronization QKD carries out equipment streams to execute stream dispatchers where the bit is continually getting new information. One runs at a decent rate from an outside QRNG source and different sudden spikes in demand for a FPGA Communicating a qubit to a QKD collector. The framework was effectively tried during a long exhibit Its strength and security. This confirmation prepares for a safer execution of QKD. Since QKD states are produced by a totally evident stochastic interaction with genuine outright security Not with explicit augmentation components. At last, it permits us to see a singular amount The transmitter incorporates arbitrary numbers and qubit age.
Abstract This paper presents the equipment and programming design that can be utilized in these frameworks which carries out pragmatic quantum key conveyance (QKD) and quantum arbitrary number age (QRNG). Plans This engineering makes the most of the capacities of the framework on a chip (SoC) that executes Programmable door cluster (FPGA) and double center CPU. Relegating time-bound errands For FPGA and CPU the executives, we have made an adaptable framework with ideal asset designation. A business off-the-rack (COTS) assessment board that incorporates the SoC. Likewise with a change For information stream, the general framework design can be utilized as QKD transmitter, QKD collector. what's more, the control and acknowledgment unit QRNG. At last, we utilized double center execution and saw the synchronization QKD carries out equipment streams to execute stream dispatchers where the bit is continually getting new information. One runs at a decent rate from an outside QRNG source and different sudden spikes in demand for a FPGA Communicating a qubit to a QKD collector. The framework was effectively tried during a long exhibit Its strength and security. This confirmation prepares for a safer execution of QKD. Since QKD states are produced by a totally evident stochastic interaction with genuine outright security Not with explicit augmentation components. At last, it permits us to see a singular amount The transmitter incorporates arbitrary numbers and qubit age.
This article presents a hardware and software architecture, which can be used in those systems that implement practical quantum key distribution (QKD) and quantum random-number generation (QRNG) schemes. This architecture fully exploits the capability of a System on a Chip (SoC), which comprehends both a field-programmable gate array (FPGA) and a dual-core CPU unit. By assigning the time-related tasks to the FPGA and the management to the CPU, we built a flexible system with optimized resource sharing on a commercial off-the-shelf (COTS) evaluation board, which includes an SoC. Furthermore, by changing the dataflow direction, the versatile system architecture can be exploited as a QKD transmitter, QKD receiver, and QRNG control-acquiring unit. Finally, we exploited the dual-core functionality and realized a concurrent stream device to implement a practical QKD transmitter, where one core continuously receives fresh data at a sustained rate from an external QRNG source, while the other operates with the FPGA to drive the qubit transmission to the QKD receiver. The system was successfully tested on a long-term run proving its stability and security. This demonstration paves the way toward a more secure QKD implementation, with fully unconditional security as the QKD states are entirely generated by a true random process and not by deterministic expansion algorithms. Eventually, this enables the realization of a standalone quantum transmitter, including both the random numbers and the qubit generation.
Our work aims to introduce an FPGA-based electronics architecture designed to enhance the security of quantum key distribution (QKD) networks. The core focus is on integrating a true random number generator (TRNG) IP in an FPGA-based QKD control electronics implemented on Xilinx’s ZYNQ UltraScale+ based FPGA boards. The work presents the challenges in integrating an existing TRNG IP with QKD FPGA design, different bit and timing requirements, the subsequent speed mismatch issues, support for multiple QKD protocols (Coherent One-Way (CoW) and Differential Phase Shift (DPS)) and user-defined QKD implementations. The integrated design also supports external QRNG/TRNG over USB/Ethernet.
Abstract In the domain of quantum-secure communications, post-processing emerges as a critical mechanism to ensure the security and integrity of the generated keys generated by quantum key distribution (QKD). However, existing post-processing frameworks often lack universality, being highly tailored to single-algorithm implementations and frequently neglecting key aspects such as system scalability and integration. To address these limitations, we present a novel system-on-chip (SoC) architecture for QKD post-processing, built around a co-designed framework featuring a RISC-V soft-core processor. This architecture incorporates core functionalities essential to QKD post-processing, including privacy amplification, information reconciliation, and high-speed communication interfaces. By leveraging the flexibility of the open-source RISC-V instruction set, the system achieves enhanced adaptability and energy efficiency. Additionally, a separated-bus architecture is employed, decoupling data and instruction buses to optimize data transfer efficiency and overall system performance, paving the way for scalable and high-throughput quantum communication systems. The system is deployed on the Xilinx Kintex Ultrascale series development board. At the Bob side, with a frame length of 16 384, the information reconciliation module and the privacy amplification module achieves throughputs of 29.73 Mbps and 131.07 Mbps, respectively.
Quantum Key Distribution (QKD) has progressed from a theoretical cryptographic concept to an emerging secure communication infrastructure technology. While early work focused on protocol security and physical-layer feasibility, current research increasingly addresses scalable network deployment, hardware acceleration, and integration with classical communication systems. As QKD expands from point-to-point links to metropolitan, backbone, and hybrid satellite–terrestrial networks, new engineering challenges arise in topology design, entropy generation, real-time key distillation, and multi-vendor interoperability. This survey provides an infrastructure-oriented review of QKD networks, examining architectural models, quantum randomness as a root of trust, FPGA and system-on-chip (SoC) based acceleration techniques, and programmable control-plane integration. Key management system architectures and standardized interfaces are analyzed to highlight their roles in enabling scalable, interoperable deployments. The paper also synthesizes major standardization efforts and deployment initiatives shaping carrier-grade QKD infrastructures. Finally, open engineering challenges, including scalability, control-plane integration, certification harmonization, and hybridization with post-quantum cryptography, are identified, positioning QKD as a foundational component of next-generation secure communication systems.
The increasing efforts by different organizations and countries regarding quantum key distribution (QKD) for secure communications are likely to result in diverse implementations for distinct users. To address this, the development of a software framework for a multi-encoding QKD system is proposed. Part of this framework are the time synchronization between transmitter and receiver, input generation for the arbitrary waveform generator (AWG) used in the implementation, as well as computing the quantum bit error rate (QBER) and secret key rate (SKR) for the employed protocol. This framework support various protocols, such as decoy-state BB84, differential phase-shift (DPS) or coherent one-way (COW), enabling a transmitter to securely exchange keys with different types of receivers. Our approach involves designing a modular and scalable architecture accommodating multiple QKD protocols to ensure compatibility and flexibility. The framework is a step towards interoperability and future-proofing in case current protocols become obsolete.
This thesis work is about the realization of hardware and software systems for Quantum Random Number Generation (QRNG) and Quantum Key Distribution (QKD). Such systems were developed to guarantee a full functionality for a broader investigation of these two cutting edge applications of Quantum Information field. The thesis describes in details both the hardware and the software that were developed for FPGA-CPU board, Time-to-Digital converter (TDC) devices and computers, along with QRNG and QKD specific applications and their results. Randy was the first FPGA-based QRNG device to be developed; it uses a light source attenuated to single-photon level and one single-photon avalanche diode (SPAD). From the sampling of the SPAD electrical signal, the device produces random numbers through dedicated generation protocols and through the Peres unbiasing algorithm in order to maximize the output generation bit rate. Furthermore, the device allows to generate real time random numbers. This feature is used for the time setting of electro-optical components for extending Wheeler’s delayed-choice experiment to space. The same techniques were applied to a second device, LinoSPAD; it combines an FPGA-chip and a CMOS-SPADs array. Moreover, in this device, a TDC improves the photon detection time accuracy. Along with a dedicated post-processing based on Zhou-Bruk algorithm, the TDC allowed to reach a final bit rate equivalent to 300 Mbit/s. As far as QKD systems are concerned, within the collaboration among the University of Padova, the Italian Space Agency (ASI) with the Matera Laser Ranging Observatory (MLRO) and the Chinese Academy of Sciences (CAS) a TDC device management software was developed. The project aim is to realize a quantum cryptographic key exchange between the Chinese satellite Micius and MLRO. The software was designed to manage the entire data acquisition synchronized with UTC time. Furthermore, another software was designed to deal with electro-optomechanical and electro-optical components. The software is aim at the time-variant compensation of the beam angular changes through the optical path. Once again, within a collaboration between ASI and University of Padova, a full free space QKD system over tenths of kilometers was developed. It required the design of various components. This work describes the QKD source along with the dedicated FPGA board design. Such board generates the electrical impulses to control the qubit laser along with the electro-optic phase and intensity modulators.