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Experimental Characterization of Google's Sycamore Quantum AI on IBM’s Quantum Computers

M. AbuGhanem

Published Jan 1, 2022• 8 citations
Publisher
DOI
10.2139/ssrn.4299338

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The exponential growth of large language models (LLMs) and deep neural networks has pushed conventional GPUbased compute infrastructures toward fundamental physical and economic limits. While graphics processing units (GPUs) remainthe dominant platform for AI training and inference, emerging hardware paradigms—particularly quantum computing processors and neuromorphic chips—promise transformative gains in energy efficiency, parallelism, and computational throughput.This paper presents a systematic comparative analysis of three leading hardware classes: high-performance GPUs (NVIDIA H100, AMD MI300X), gate-based quantum processors (IBM Eagle, Google Sycamore), and neuromorphic processors (Intel Loihi 2, IBM TrueNorth). We evaluate these architectures across five critical dimensions: raw throughput, energy efficiency, scalability, programmability, and readiness for production AI workloads. Our analysis demonstrates that while GPUs maintain decisive advantages for transformer-based workloads through 2027, quantum annealers exhibit compelling potential for combinatorial optimization in neural architecture search, and neuromorphic chips offer orders-of-magnitude improvements in energy efficiency for sparse, event-driven inference tasks. We conclude with a proposed hybrid hardware stack and a technology readiness roadmap for the 2025–2035 decade, offering practical guidance for AI systems architects and researchers navigating the post-Moore’s Law compute landscape.

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Abstract The potential of achieving computational hardware with quantum advantage depends heavily on the quality of quantum gate operations. However, the presence of imperfect two-qubit gates poses a significant challenge and acts as a major obstacle in developing scalable quantum information processors. Google’s Quantum AI and collaborators claimed to have conducted a supremacy regime experiment. In this experiment, a new two-qubit universal gate called theSycamoregate is constructed and employed to generate random quantum circuits (RQCs), using a programmable quantum processor with 53 qubits. These computations were carried out in a computational state space of size 9×10159 \times 10^{15}9×1015 9×1015 . Nevertheless, even in strictly-controlled laboratory settings, quantum information on quantum processors is susceptible to various disturbances, including undesired interaction with the surroundings and imperfections in the quantum state. To address this issue, we conduct both quantum state tomography (QST) and quantum process tomography (QPT) experiments on Google’sSycamoregate using different artificial architectural superconducting quantum computer. Furthermore, to demonstrate how errors affect gate fidelity at the level of quantum circuits, we design and conduct full QST experiments for the five-qubit eight-cycle circuit, which was introduced as an example of the programability of Google’sSycamorequantum processor. These quantum tomography experiments are conducted in three distinct environments: noise-free, noisy simulation, and on IBM Quantum’s genuine quantum computer. Our results offer valuable insights into the performance of IBM Quantum’s hardware and the robustness ofSycamoregates within this experimental setup. These findings contribute to our understanding of quantum hardware performance and provide valuable information for optimizing quantum algorithms for practical applications.
Quantum computing is evolving as a revolutionary technology, capable of solving complex problems that are far beyond the reach of traditional computers. Google and China as the global leaders in the race taking their distinct paths with their research and development strategies. Through the Sycamore quantum processor and its Gemini AI, Google focuses on taking the artificial intelligence to the next level, improving optimization, and building practical tools for commercial use. From the Google’s work, especially with the Sycamore quantum processor and its Gemini AI ecosystem, it focuses on advancing artificial intelligence, improving optimization, and building practical tools for commercial use. In contrast, China’s progress, demonstrated through systems like the Jiuzhang photonic platform and the superconducting Zuchongzhi processor, is closely tied to national objectives such as cybersecurity, secure communication, and long-term strategic advantage. This literature review studies the recent researches to compare the two approaches to understand their motivations and examine how their innovations are influencing the future of computing. It also points out existing limitations, challenges in scaling hardware and integrating quantum computing with AI systems. Finally, it emphasizes the key areas where further researches are needed to sustain progress and unleash the full potential of quantum technologies.
The exponential growth of large language models (LLMs) and deep neural networks has pushed conventional GPUbased compute infrastructures toward fundamental physical and economic limits. While graphics processing units (GPUs) remainthe dominant platform for AI training and inference, emerging hardware paradigms—particularly quantum computing processors and neuromorphic chips—promise transformative gains in energy efficiency, parallelism, and computational throughput.This paper presents a systematic comparative analysis of three leading hardware classes: high-performance GPUs (NVIDIA H100, AMD MI300X), gate-based quantum processors (IBM Eagle, Google Sycamore), and neuromorphic processors (Intel Loihi 2, IBM TrueNorth). We evaluate these architectures across five critical dimensions: raw throughput, energy efficiency, scalability, programmability, and readiness for production AI workloads. Our analysis demonstrates that while GPUs maintain decisive advantages for transformer-based workloads through 2027, quantum annealers exhibit compelling potential for combinatorial optimization in neural architecture search, and neuromorphic chips offer orders-of-magnitude improvements in energy efficiency for sparse, event-driven inference tasks. We conclude with a proposed hybrid hardware stack and a technology readiness roadmap for the 2025–2035 decade, offering practical guidance for AI systems architects and researchers navigating the post-Moore’s Law compute landscape.