In EDA, Reversible logic has its applications in designing computer graphics, digital signal processing, quantum computing, nanotechnology and cryptography. It is a prospective design style in quantum computing and modern nanotechnology. Although noteworthy proposals have been put forth towards defining new reversible logic gates and sub units of ALUs, design of efficient Multiplier block remains crucial to the realization of a high-performance Reversible Logic ALU that can be leveraged by Deep Neural Networks for high performance MAC operations. This paper proposes the design and comparison of a component scalable Reversible Logic Multiplier using the proposed SAK gate. The verification and simulation have been carried out using Vivado® by Xilinx and further implemented on an Artix®-7 based cost effective FPGA. The proposed design has 27% lesser Gate Count and 12.5% lesser Quantum Cost compared to prior designs.
In EDA, Reversible logic has its applications in designing computer graphics, digital signal processing, quantum computing, nanotechnology and cryptography. It is a prospective design style in quantum computing and modern nanotechnology. Although noteworthy proposals have been put forth towards defining new reversible logic gates and sub units of ALUs, design of efficient Multiplier block remains crucial to the realization of a high-performance Reversible Logic ALU that can be leveraged by Deep Neural Networks for high performance MAC operations. This paper proposes the design and comparison of a component scalable Reversible Logic Multiplier using the proposed SAK gate. The verification and simulation have been carried out using Vivado® by Xilinx and further implemented on an Artix®-7 based cost effective FPGA. The proposed design has 27% lesser Gate Count and 12.5% lesser Quantum Cost compared to prior designs.
Reversible logic provides a foundation for nextgeneration computing systems, particularly in quantum and emerging nanotechnology-based architectures. Unlike conventional logic, reversible gates preserve information and support backward computation, making them crucial for designing quantum circuits. This paper introduces a reversible Arithmetic and Logic Unit (ALU) that performs eight fundamental operations-AND, OR, NOT, XOR, addition, subtraction, increment, and decrement-using Fredkin, Peres, TR, and modified Fredkin gates. A dedicated control unit manages operation selection, ensuring functional flexibility and circuit efficiency. The proposed design achieves significant improvements by minimizing ancilla inputs, quantum cost and garbage outputs, resulting in a total quantum cost of 71 and contains 16 reversible gates and 14 garbage outputs. The architecture was modeled and verified using Xilinx Vivado HLS and ISE 14.7, and implemented on the Nexys A7 (Artix-7) FPGA platform. Comparative analysis demonstrates better efficiency than existing reversible ALU designs, establishing the proposed circuit as a strong candidate for quantum computing and other advanced computing paradigms.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
In recent years, reversible logic has emerged as a promising technology withapplications spanning low-power CMOS, quantum computing, nanotechnology, andoptical computing. Quantum computing, in particular, relies on reversible logic for itsrealization. The construction of low-power and low-loss computational structures iscrucial for developing arithmetic circuits used in quantum computation, nanotechnology,and other low-power digital circuits. This work presents optimized one-digit BCD addersand carries skip BCD adders using new reversible logic gates. The proposed approachaims to minimize quantum cost and optimize performance compared to existing circuits,focusing on reducing the number of reversible gates used and minimizing garbage outputsproduced. The objective is to design faster BCD adders and provide a foundation forbuilding the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work isimplemented using Hardware Description Language (HDL), with Simulation & Synthesisconducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. Thisresearch contributes to the advancement of efficient and high-performance arithmeticcircuits suitable for emerging technologies such as quantum computing andnanotechnology.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
Reversible logic is now employed in low-power CMOS circuits, optical data processing, DNA calculations, biological studies, quantum circuits, and nanotechnology.When building quantum computers, for example, the use of reversible logic is unavoidable.The structure of a reversible logic circuit is far more complex than that of an irreversible logic circuit.The multiplication operation is regarded as one of the most crucial in the ALU unit.In this paper, the Wallace tree method is utilized to minimize the depth of circuits in 8x 8 reversible unsigned multiplier circuits.The proposed design is an attempt to enhance design factors including the number of gates, garbage outputs, constant inputs, and quantum cost for an 8-bit Wallace Tree multiplier using reversible logic.The Proposed design offers 27% less quantum cost compared to the existing 8-bit Wallace tree multiplier design.
This paper presents the design and implementation of a reversible 4×4 enhanced multiplier using quantum logic principles. The proposed architecture employs Toffoli and Peres gates to realize reversible AND gates and full adders, respectively, ensuring minimal energy dissipation in accordance with Landauer's principle. A layered structure is introduced to improve computation speed and modular scalability while maintaining reversibility. The design effectively reduces garbage outputs and constant inputs, which are critical performance parameters in reversible computing. Simulation results verify the functional correctness of the multiplier and demonstrate its potential for application in quantum computing, low-power VLSI design, and nanotechnology-based systems. The modular nature of the architecture also supports scalability for higher-order multipliers with minimal design overhead.