Quantum computing is developing rapidly, especially those systems based on superconductors, electron or hole spin in semiconductors[1], which generally operate at sub-1 K temperatures[2]. And the classical electronics control system for qubits at room temperature meets increasing challenges, due to utter interconnect complexity, poor system reliability, and cost. Integrating part or all of the interface electronics inside the dilution refrigerator becomes an promising branch. For the convenience of cryo-electronics testing and establishing of the whole electronics control system for quantum computing at cryogenic temperatures, we describe the operation of some commercial devices at cryogenic temperatures, including two FPGAs respectively on 28 nm and 16 nm process node and three GaAs RF switches.
Quantum computing is developing rapidly, especially those systems based on superconductors, electron or hole spin in semiconductors[1], which generally operate at sub-1 K temperatures[2]. And the classical electronics control system for qubits at room temperature meets increasing challenges, due to utter interconnect complexity, poor system reliability, and cost. Integrating part or all of the interface electronics inside the dilution refrigerator becomes an promising branch. For the convenience of cryo-electronics testing and establishing of the whole electronics control system for quantum computing at cryogenic temperatures, we describe the operation of some commercial devices at cryogenic temperatures, including two FPGAs respectively on 28 nm and 16 nm process node and three GaAs RF switches.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine.
Quantum computing holds the potential to solve problems beyond the capabilities of classical computers. However, realizing practical large-scale quantum computers faces critical challenges, including the key bottleneck in wiring quantum processors operating at cryogenic temperatures to their room temperature control electronics. This article explores cryo-CMOS ICs as an enabling technology to circumvent such a wiring bottleneck. After reviewing the basics of quantum computing and the behavior of CMOS devices at cryogenic temperatures, the requirements for the interface electronics for superconducting and semiconductor qubits are discussed, and state-of-the-art cryo-CMOS circuit solutions are briefly described, including a few hints to other qubit platforms. Finally, the article concludes with an overview of future challenges to be addressed to realize the vision of cryo-CMOS technology as an enabler of large-scale quantum computers with practical applications.
Cryogenic CMOS control and readout electronics for quantum computing using superconducting qubits offers several potential advantages versus the use of room temperature electronics, including reduced wiring and lower cost per control channel. The development and practical implementation of such electronics at a mass-production scale for systems with tens of thousands of channels, however, requires circuit characterization in the target cryogenic use environment and with interfaces as close as possible to those that will be used in a real quantum machine. The cryogenic use environment and interfaces for test are usually far from the almost ideal conditions that can be achieved in a regular cryogenic probe station. In this paper, we describe a new testbed for the characterization of CMOS circuits at cryogenic temperatures that solves some of these problems.
Quantum computers can provide exponential speedup in solving certain computational problems pertaining to drug discovery, cybersecurity, weather forecasting, etc. Although a quantum computer with just 50-qubits has been shown to surpass the computing power of the best supercomputers in specific applications, millions of qubits would be required for useful practical applications. One of the biggest obstacles in scaling from 50 qubits to millions of qubits is the interconnect bottleneck between solid-state qubits operating at 20 milliKelvin inside a dilution refrigerator and control electronics outside the dilution refrigerator connected via long coaxial cables. A 50-qubit processor requires hundreds of cables, digital to analog converters, mixers and amplifiers, clearly challenging the scalability of the system. The goal of this research is to build scalable quantum computers by operating CMOS control electronics inside the dilution refrigerator in proximity to quantum processors. The dissertation covers a broad aspect of cryogenic integrated circuit design spanning across devices, circuits and systems.