QUANTUM COMPUTATION IN SILICON — DEVICE MODELING, TRANSPORT AND FAULT-TOLERANCE

Adriano Barenco

Lloyd C. L. Hollenberg

The Kane concept of quantum computation using single phosphorus donors in silicon has revolutionized the way we think about P -doped silicon devices. However, because of the enormous effort required in fabricating such devices using single atom techniques, detailed modeling and assessment of fault-tolerant operation is required to determine and optimize the scalability, and indeed feasibility, of such a vision.

Sven M. J. Rogge

David Peter Divincenzo

M. E. Hawley, Geoff W. Brown, G. P. Berman

Ashley M. Stephens, Lloyd C. L. Hollenberg

A two-dimensional architecture is considered in which logical qubits are stored on isolated cells. Intra-logical transport is via nearest-neighbor SWAP operations and inter-logical operation is via short-distance qubit transport. Non-local quantum circuitry is adapted to this architecture to implement fault tolerant quantum computation under the [[7,1,3]] quantum code. The CNOT gate threshold for this architecture is estimated and is presented as an explicit physical gate failure rate in a number of common physical settings.