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FAULT TOLERANT QUANTUM COMPUTATION ON ISOLATED LOGICAL CELLS

Ashley M. Stephens, Lloyd C. L. Hollenberg

Published Jan 1, 2006• 0 citations
OpenAlex

Abstract

A two-dimensional architecture is considered in which logical qubits are stored on isolated cells. Intra-logical transport is via nearest-neighbor SWAP operations and inter-logical operation is via short-distance qubit transport. Non-local quantum circuitry is adapted to this architecture to implement fault tolerant quantum computation under the [[7,1,3]] quantum code. The CNOT gate threshold for this architecture is estimated and is presented as an explicit physical gate failure rate in a number of common physical settings.

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Latency in local, two-dimensional, fault-tolerant quantum computing

(pp0666-0682) F.M. Spedalieri and V.P. Roychowdhury We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane's 7-qubit code~\cite{svore2007a}. Furthermore, the error threshold is also improved to $2.02 \times 10^{-5}$, when memory errors are taken to be one tenth of the gate error rates.

Quantum Information and Computation•Jul 1, 2009•21 citations
A two-dimensional architecture is considered in which logical qubits are stored on isolated cells. Intra-logical transport is via nearest-neighbor SWAP operations and inter-logical operation is via short-distance qubit transport. Non-local quantum circuitry is adapted to this architecture to implement fault tolerant quantum computation under the [[7,1,3]] quantum code. The CNOT gate threshold for this architecture is estimated and is presented as an explicit physical gate failure rate in a number of common physical settings.
Assuming an array that consists of two parallel lines of qubits and that permits only nearest neighbor interactions, we construct physical and logical circuitry to enable universal fault tolerant quantum computation under the [[7,1,3]][[7,1,3]][[7,1,3]] quantum code. A rigorous lower bound to the fault tolerant threshold for this array is determined in a number of physical settings. Adversarial memory errors, two-qubit gate errors and readout errors are included in our analysis. In the setting where the physical memory failure rate is equal to one-tenth of the physical gate error rate, the physical readout error rate is equal to the physical gate error rate, and the duration of physical readout is ten times the duration of a physical gate, we obtain a lower bound to the asymptotic threshold of 1.96×10−61.96\times10^{-6}1.96×10−6.
We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane's 7-qubit code (K. M. Svore, D. P. DiVincenzo, and B. M. Terhal, Quantum Information & Computation {\bf 7}, 297 (2007)). Furthermore, the error threshold is also improved to 2.02×10−52.02 \times 10^{-5}2.02×10−5, when memory errors are taken to be one tenth of the gate error rates.
We describe in detail how to perform universal fault-tolerant quantum computation on a two-dimensional color code, making use of only nearest neighbor interactions. Three defects (holes) in the code are used to represent logical qubits. Triple-defect logical qubits are deformed into isolated triangular sections of color code to enable transversal implementation of all single logical qubit Clifford group gates. Controlled-NOT (CNOT) is implemented between pairs of triple-defect logical qubits via braiding.
We consider a model of quantum computation in which the set of operations is limited to nearest-neighbor interactions on a 2D lattice. We model movement of qubits with noisy SWAP operations. For this architecture we design a fault-tolerant coding scheme using the concatenated [[7,1,3]] Steane code. Our scheme is potentially applicable to ion-trap and solid-state quantum technologies. We calculate a lower bound on the noise threshold for our local model using a detailed failure probability analysis. We obtain a threshold of 1.85 x 10^-5 for the local setting, where memory error rates are one-tenth of the failure rates of gates, measurement, and preparation steps. For the analogous nonlocal setting, we obtain a noise threshold of 3.61 x 10^-5. Our results thus show that the additional SWAP operations required to move qubits in the local model affect the noise threshold only moderately.
We consider a model of quantum computation in which the set of operations is limited to nearest-neighbor interactions on a 2D lattice. We model movement of qubits with noisy SWAP operations. For this architecture we design a fault-tolerant coding scheme using the concatenated [[7,1,3]] Steane code. Our scheme is potentially applicable to ion-trap and solid-state quantum technologies. We calculate a lower bound on the noise threshold for our local model using a detailed failure probability analysis. We obtain a threshold of 1.85 x 10^-5 for the local setting, where memory error rates are one-tenth of the failure rates of gates, measurement, and preparation steps. For the analogous nonlocal setting, we obtain a noise threshold of 3.61 x 10^-5. Our results thus show that the additional SWAP operations required to move qubits in the local model affect the noise threshold only moderately.
(pp0666-0682) F.M. Spedalieri and V.P. Roychowdhury We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane's 7-qubit code~\cite{svore2007a}. Furthermore, the error threshold is also improved to 2.02×10−52.02 \times 10^{-5}2.02×10−5, when memory errors are taken to be one tenth of the gate error rates.