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Proceedings - International Symposium on Computer Architecture/Proceedings

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures

Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin

Published Jul 27, 2005• 41 citations
Publisher

Abstract

The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.

DOI
10.1109/isca.2005.10

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The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
The theoretical study of quantum computation has yielded efficient algorithms for traditionally very hard problems. Correspondingly, the experimental work on technologies for implementing quantum computers has yielded many of the essential discrete components. Combining these components to produce an efficient and accurate quantum architecture is an open problem and exploring this design space requires an efficient evaluation framework. To date, all such frameworks have been either highly theoretical (ignoring vital issues like spatial constraints, resource contention, and the durative nature of quantum operations), or limited to systems with less than 40 qubits because of reliance on simulating the exact quantum state of qubits in the system. To address these issues the authors present QUALE, a set of tools for the design and analysis of microarchitectures for ion-trap quantum computers. QUALE allows the user to specify a quantum program in an existing quantum language, apply error correction, schedule the resulting computation on a proposed layout, and determine an upper bound on the expected accuracy of the resulting computation. By conducting analysis on a program-architecture pair QUALE takes into account realistic architectural constraints; by targeting simulation to error as opposed to the whole quantum state, QUALE is able to efficiently simulate large systems containing thousands of quantum bits.
The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.
Quantum computing is at the cusp of showing relevance for real-world problems. However, currently available devices are small in scale, and hardware demonstrations have shown limited applicability to scientific and commercial problems of interest. In this work, we investigate a set of application-specific noisy intermediate-scale quantum (NISQ) algorithms varying in size from 4-80 qubits, and use these benchmarks to evaluate trade-offs in the design of trapped ion quantum computing architectures. We have developed a tool-chain consisting of architecture specific compilation and simulation tools and used these tools to target five different candidate trapped ion quantum computing architectures. Using our tool-chain, we can estimate metrics such as application run-times and overhead. Additionally, we use our tools to determine the critical operations of an architecture and to study the sensitivity to architectural constraints in particular implementations. Our tools are designed to be flexible, allowing us to study a broad range of benchmarks, hardware architectures, physical constraints, and operation timing.
We design and implement a SIMD scheduler that returns the distribution of quantum operations when taking into account communication and layout constraints. We define the ion-motion path interface for trapped ion quantum computing architectures and analyze the design constraints involved in assembling the control circuitry necessary to implement this interface. Finally, we describe an Instruction Set Architecture (ISA) that we can use to optimize and provide a library of fault-tolerant building blocks for scalable quantum computation.
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a fault-tolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024-bit number with a baseline budget of 1.5 million qubits. We show that a trapped-ion quantum computer designed with twice as many qubits and one-tenth of the baseline infidelity of the communication channel can factor a 2,048-bit integer in less than 5 months.