The theoretical study of quantum computation has yielded efficient algorithms for traditionally very hard problems. Correspondingly, the experimental work on technologies for implementing quantum computers has yielded many of the essential discrete components. Combining these components to produce an efficient and accurate quantum architecture is an open problem and exploring this design space requires an efficient evaluation framework. To date, all such frameworks have been either highly theoretical (ignoring vital issues like spatial constraints, resource contention, and the durative nature of quantum operations), or limited to systems with less than 40 qubits because of reliance on simulating the exact quantum state of qubits in the system. To address these issues the authors present QUALE, a set of tools for the design and analysis of microarchitectures for ion-trap quantum computers. QUALE allows the user to specify a quantum program in an existing quantum language, apply error correction, schedule the resulting computation on a proposed layout, and determine an upper bound on the expected accuracy of the resulting computation. By conducting analysis on a program-architecture pair QUALE takes into account realistic architectural constraints; by targeting simulation to error as opposed to the whole quantum state, QUALE is able to efficiently simulate large systems containing thousands of quantum bits.
The theoretical study of quantum computation has yielded efficient algorithms for traditionally very hard problems. Correspondingly, the experimental work on technologies for implementing quantum computers has yielded many of the essential discrete components. Combining these components to produce an efficient and accurate quantum architecture is an open problem and exploring this design space requires an efficient evaluation framework. To date, all such frameworks have been either highly theoretical (ignoring vital issues like spatial constraints, resource contention, and the durative nature of quantum operations), or limited to systems with less than 40 qubits because of reliance on simulating the exact quantum state of qubits in the system. To address these issues the authors present QUALE, a set of tools for the design and analysis of microarchitectures for ion-trap quantum computers. QUALE allows the user to specify a quantum program in an existing quantum language, apply error correction, schedule the resulting computation on a proposed layout, and determine an upper bound on the expected accuracy of the resulting computation. By conducting analysis on a program-architecture pair QUALE takes into account realistic architectural constraints; by targeting simulation to error as opposed to the whole quantum state, QUALE is able to efficiently simulate large systems containing thousands of quantum bits.
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.
As the complexity of quantum computers increases, typical architectural issues such as communication, layout, and efficient design need to be addressed. This document addresses some basic architectural ideas for quantum computers.
To be useful in reasonable calculations, quantum states will need constant error correction. This need guides how best to lay out physical components to minimize error-correction overhead. I propose a layout that minimizes communication overhead, and discuss the implementation of error-correction algorithms on that layout. I compare the cost overhead of purely local communication to communication by teleportation, and calculate the break-even point at which teleportation becomes efficient.
Additionally, the overhead of error correction can be reduced by using a memory hierarchy to more efficiently store data not currently being computed on. The main requirement is the same as for a classical computer's cache: temporal locality. I show that an important quantum routine can be rearranged to take advantage of a small quantum memory cache, and compute the achieved savings.
In a quantum system, complex operators are built up from the basic operators allowed by a given technology model. I show that the set of operators required to implement any complex operator in an error-corrected system can be approximated to arbitrary precision, given two elementary operators. I give results for all the operators in the set.
Finally, I examine methods to initialize a quantum system. Quantum operators are reversible, so data cannot simply be written over. Instead, initialization entails compressing the entropy of a set of quantum bits into a small subset of those bits, leaving the rest of the bits in a known, non-random state. I examine three such compression algorithms. The best of these itself requires a pool of known states, and so cannot be used directly. The other two algorithms, however, produce less-than-optimal results. I explore why they produce suboptimal results, and propose that one of the suboptimal algorithms be used to compress the entropy of a subsystem, using the resulting known state to run the optimal algorithm.
The optimal design of a fault-tolerant quantum computer involves finding an appropriate balance between the burden of large-scale integration of noisy components and the load of improving the reliability of hardware technology. This balance can be evaluated by quantitatively modeling the execution of quantum logic operations on a realistic quantum hardware containing limited computational resources. In this work, we report a complete performance simulation software tool capable of (1) searching the hardware design space by varying resource architecture and technology parameters, (2) synthesizing and scheduling a fault-tolerant quantum algorithm within the hardware constraints, (3) quantifying the performance metrics such as the execution time and the failure probability of the algorithm, and (4) analyzing the breakdown of these metrics to highlight the performance bottlenecks and visualizing resource utilization to evaluate the adequacy of the chosen design. Using this tool, we investigate a vast design space for implementing key building blocks of Shor’s algorithm to factor a 1,024-bit number with a baseline budget of 1.5 million qubits. We show that a trapped-ion quantum computer designed with twice as many qubits and one-tenth of the baseline infidelity of the communication channel can factor a 2,048-bit integer in less than 5 months.
Efforts to build quantum computers using ion-traps have demonstrated all elementary qubit operations necessary for scalable implementation. Modular architectures have been proposed to construct modest size quantum computers with up to 104- 106qubits using technologies that are available today (MUSIQC architecture). Concrete scheduling procedure to execute a given quantum algorithm on such a hardware is a significant task, but existing quantum CAD tools generally do not account for the underlying connectivity of the qubits or the limitation on the hardware resources available for the scheduling. We present a scheduler and performance simulator that fully accounts for these resource constraints, capable of estimating the execution time and error performances of executing a quantum circuit on the hardware. We outline the construction of tool components, and describe the process of mapping the qubits to ions and scheduling the physical gates in the MUSIQC architecture. Using this tool, we quantify the trade-off between hardware resource constraints and performance of the computer and show that at an expense of x fold increase in latency, a minimum of 1.6x resource reduction is possible for executing a three-qubit Bernstein-Vazirani algorithm encoded using Steane code.