We design and implement a SIMD scheduler that returns the distribution of quantum operations when taking into account communication and layout constraints. We define the ion-motion path interface for trapped ion quantum computing architectures and analyze the design constraints involved in assembling the control circuitry necessary to implement this interface. Finally, we describe an Instruction Set Architecture (ISA) that we can use to optimize and provide a library of fault-tolerant building blocks for scalable quantum computation.
We design and implement a SIMD scheduler that returns the distribution of quantum operations when taking into account communication and layout constraints. We define the ion-motion path interface for trapped ion quantum computing architectures and analyze the design constraints involved in assembling the control circuitry necessary to implement this interface. Finally, we describe an Instruction Set Architecture (ISA) that we can use to optimize and provide a library of fault-tolerant building blocks for scalable quantum computation.
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
Exploiting recent advances in quantum trapped-ion technologies, we propose a scalable, fault-tolerant quantum computing architecture that overcomes the fundamental challenges of building a full-scale quantum computer and leaves the fabrication a daunting but primarily an engineering concern. Using a hierarchical array-based design and a quantum teleportation communication protocol, we are able to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution. In particular, we present a reconfigurable quantum circuit substrate, or "quantum FPGA'' (qFPGA) which allows efficient implementation of universal quantum gates and error correction. We use this qFPGA as a basic building block for an array structure that scalably provides communication channels and quantum resource distribution. We exploit a hierarchical combination of ballistic transport of data ions and quantum teleportation to reduce the cost of reliable communication from exponential to polynomial in distance. By using a set of simulation tools we are able to evaluate a hypothetical design of a future general purpose quantum computer and describe the execution of a fault-tolerant Toffoli gate construction. Without considering classical control constraints and assuming best-possible ion-trap parameters our computer consists of level 2 encoded qubits with the Steane \ecc code tightly connected by the teleportation interconnect, and capable of executing a fault-tolerant Toffoli gate in roughly 2.3 seconds. This translates to factoring a 128-bit number in slightly over 40 hours in circuits dominated by Toffoli gates.
The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits.
Efforts to build quantum computers using ion-traps have demonstrated all elementary qubit operations necessary for scalable implementation. Modular architectures have been proposed to construct modest size quantum computers with up to 104- 106qubits using technologies that are available today (MUSIQC architecture). Concrete scheduling procedure to execute a given quantum algorithm on such a hardware is a significant task, but existing quantum CAD tools generally do not account for the underlying connectivity of the qubits or the limitation on the hardware resources available for the scheduling. We present a scheduler and performance simulator that fully accounts for these resource constraints, capable of estimating the execution time and error performances of executing a quantum circuit on the hardware. We outline the construction of tool components, and describe the process of mapping the qubits to ions and scheduling the physical gates in the MUSIQC architecture. Using this tool, we quantify the trade-off between hardware resource constraints and performance of the computer and show that at an expense of x fold increase in latency, a minimum of 1.6x resource reduction is possible for executing a three-qubit Bernstein-Vazirani algorithm encoded using Steane code.
We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as 10−8 with the [[31,1,7]] color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.