In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.
In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.
The ColdFlux project, within the IARPA SuperTools program, aims to develop an open-source EDA tool suite for superconductor circuits, with focus on Rapid single flux quantum (RSFQ) and Adiabatic quantum-flux-parametron (AQFP) logic. The functionality of the ColdFlux tool suite is validated through the development of ready-to-use cell libraries. The process of establishing the open-source ColdFlux RSFQ cell library is documented, along with the set of EDA tools developed within the project required for each step. This includes the initial cell design using phase-based equations, circuit simulation, operating margin analysis, and cell parameter optimization. The row-based layout architecture for the RSFQ cell library is also presented. Several of the designed RSFQ cells are placed within test circuits and fabricated through the MIT-LL SFQ5ee fabrication process. We present the measured results for these test circuits and discuss design efficiency, potential improvements, and future work.