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情報処理学会論文誌 論文誌トランザクション

A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule (IPSJ Transactions on System LSI Design Methodology Vol.2)

Wen Ji, Xing Li, Takeshi Ikenaga

Published Apr 1, 2009• 0 citations
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This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) the column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently; and (ii) the proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead
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