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IEICE Technical Report; IEICE Tech. Rep.

Partially-parallel decoder based on high-efficiency message-passing schedule for irregular LDPC code

Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Published Feb 28, 2007• 0 citations
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In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences•Apr 1, 2006•10 citations
Schedule is the order of passing messages between vertices of the bipartite graph defining an LDPC code in the process of decoding. Schedules affect the rate of decoding convergence. New efficient generalized serial schedules are described and analyzed, exhibiting significantly faster convergence compared to previously known schedules. For the proposed schedules, combinatorial and probabilistic analysis is presented, explaining the fast convergence observed in simulations. Using it, LDPC ensembles for which significantly better convergence rates can be achieved are identified. Specific code constructions from lifted graphs are further proposed, efficiently supporting the schedules. Examples based on regular LDPC codes are provided, in which the schedules achieve convergence speedup factors of up to 6 in comparison with the flooding schedule. Higher speedup factors are predicted by the analysis for irregular codes.
In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.