In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.
In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.
In this article, clockless circuits of the two basic logic gates, namely,andandorgates, are designed using the quantum phase slip junction (QPSJ). In the previously designed (existing) circuits of these gates, there is an internal clock pulse source in the output branch, which is necessary for proper gate operation. When the existingandandorgates have to be connected to another gate, this internal clock pulse becomes a series between their outputs and the input of the next gate. As a result, the internal clock pulse must be provided by a separate source, but synchronized to the system clock pulse (which is needed for synchronization of the inputs). This increases the design complexity. By using the proposed clocklessandandorgates, the mentioned design complexity is removed. In addition, the proposed clockless gates have less number of QPSJs than the existing ones, which allows less occupied area on the chip, a higher operation frequency, and smaller dynamic power dissipation.
Quantum phase slip junction (QPSJ) can offer very low power switching operation and represent near adiabatic switching operation for using in designing of the reversible logic gates. The reversible gates have logical reversibility, where the inputs can be logically reconstructed from the outputs and no data is lost, and physical (adiabatic) reversibility, where the energy dissipation can be decreased even below the Landauer limit. In this manuscript, for the first time, designing of the QPSJ-based basic reversible gates, namely Feynman, Toffoli, Peres and Fredkin, from the logical reversibility point of view is represented. The main logic function in these gates is the XOR function. First, a new two-input QPSJ-based XOR gate with simple circuit is designed in which the outputs of the previous gate can be connected directly to its inputs without the need for splitter lines. Second, the proposed XOR gate is used to design the Feynman and Toffoli gates. Further, the Peres and Fredkin gates are designed by using the proposed Feynman and Toffoli gates. Proper operation of the proposed gates are verified by simulation results. Logical reversibility of the Feynman and Toffoli gates is verified by cascading them and operating their logical function two times, i.e.f(f(x))=x.
Quantum phase slip (QPS) junction can act as a superconductor switch when a voltage pulse larger than its critical voltage is applied to it. As a result, a current pulse with an area equal to 2e(or multiples of 2e) flows across the junction, and the junction switches from zero to one in the charge-base logic. For having a proper operation simulation of the QPS junction, it should be overdamped, and the damping factor should be less than one. Physical parameters of the QPS junction, namely, the normal resistance, the kinetic inductance, and the critical voltage, can affect the overdamping condition and switching behavior of the junction, as well as the damping factor. The basic block for designing the QPS logic gates is the charge island. By different and proper connections of the charge islands, basic QPSand, or, andxorlogic gates are designed. Generally, each of these gates has its own circuit and junction parameters for proper operation. In this manuscript, a universal QPS logic gate is proposed that can perform basicand, or, andxorBoolean functions by proper selection of parameters for QPS junctions in the case of each Boolean function. This universal QPS logic gate can simplify the design the complicated QPS logic circuits, since only the parameters of each junction have to be properly selected for achieving the desired Boolean function, and the gate circuit topology remains unchanged.
Superconducting digital computing systems, primarily involving Josephson junctions are actively being pursued as high performance and low energy dissipating alternatives to CMOS-based technologies for petascale and exascale computers, although several challenges still exist in overcoming barriers to practically implement these technologies. In this paper, we present an alternative superconducting logic structure: quantized charge-based logic circuits using quantum phase-slip junctions, which have been identified as dual devices to Josephson junctions. Basic principles of logic implementation using quantum phase-slips are presented in simulations with the help of a SPICE model that has been developed for the quantum phase-slip structures. Circuit elements that form the building blocks for complex logic circuit design are introduced. Two different logic gate designs: or gate and xor gate are presented to demonstrate the usage of the building blocks introduced.
A quantum phase slip junction (QPSJ) based direct inverter gate is proposed in this article for the first time. The proposed inverter is simpler than the QPSJ-based inverter designed indirectly by using a two-input xor gate with specific input conditions. In the indirect inverter, one of the two inputs of the xor gate must be set to the clock pulse in order to perform the true inverter operation. However, the proposed direct inverter has only one input to which the input voltage can be applied directly, and therefore, it has a simpler structure with fewer elements that occupies less area on the chip. The true operation of the proposed inverter is verified by feeding its input with the standard pseudorandom binary sequence 3 and connecting its output to the next gate to test its ability for driving the next gate.
Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.