Superconducting digital computing systems, primarily involving Josephson junctions are actively being pursued as high performance and low energy dissipating alternatives to CMOS-based technologies for petascale and exascale computers, although several challenges still exist in overcoming barriers to practically implement these technologies. In this paper, we present an alternative superconducting logic structure: quantized charge-based logic circuits using quantum phase-slip junctions, which have been identified as dual devices to Josephson junctions. Basic principles of logic implementation using quantum phase-slips are presented in simulations with the help of a SPICE model that has been developed for the quantum phase-slip structures. Circuit elements that form the building blocks for complex logic circuit design are introduced. Two different logic gate designs: or gate and xor gate are presented to demonstrate the usage of the building blocks introduced.
Superconducting digital computing systems, primarily involving Josephson junctions are actively being pursued as high performance and low energy dissipating alternatives to CMOS-based technologies for petascale and exascale computers, although several challenges still exist in overcoming barriers to practically implement these technologies. In this paper, we present an alternative superconducting logic structure: quantized charge-based logic circuits using quantum phase-slip junctions, which have been identified as dual devices to Josephson junctions. Basic principles of logic implementation using quantum phase-slips are presented in simulations with the help of a SPICE model that has been developed for the quantum phase-slip structures. Circuit elements that form the building blocks for complex logic circuit design are introduced. Two different logic gate designs: or gate and xor gate are presented to demonstrate the usage of the building blocks introduced.
Superconducting circuits that operate by propagation of small voltage or current pulses, corresponding to propagation of single flux or charge quantum, are naturally suited for implementing spiking neuron circuits. Quantum phase-slip junctions (QPSJs) are 1-D superconducting nanowires that have been identified as exact duals to Josephson junctions, based on charge-flux duality in Maxwell’s equations. In this paper, a superconducting quantized-charge circuit element, formed using quantum phase-slip junctions, is investigated for use in high-speed, low-energy superconducting spiking neuron circuits. By means of a SPICE model developed for QPSJs, operation of this superconducting circuit to produce and transport quantized charge pulses, in the form of current pulses, is demonstrated. The resulting quantized-charge-based operation emulates spiking neuron circuits for brain-inspired neuromorphic applications. Additionally, to further demonstrate the operation of QPSJ-based neuron circuits, a QPSJ-based integrate and fire neuron circuit is introduced, along with simulation results using WRSPICE. Estimates for operating speed and power dissipation are provided and compared to Josephson junction and CMOS-based spiking neuron circuits. Current challenges are also briefly mentioned.
In this paper, we explore a new set of circuits that incorporate both single-flux-quantum and quantized charge-based complementary quantum logic circuits. Circuits that convert single-flux quantum voltage pulses to quantized charge pulses and vice versa, leading to circuits that simplify logic and integration operations of individual flux and charge-based logic circuits, are introduced. These include fan-out circuits that enable single flux input to several charge outputs as well as control gate circuit with charge input controlling flux output. The operation of these circuits is demonstrated in simulations using WRSPICE. An XOR gate implementation is presented as an example to illustrate the operation of these circuits. The developed complementary quantum logic circuits show promise for higher power efficiency and simpler design in the form of fewer junctions for a given logic implementation, leading to the possibility of higher integration density.
In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.
Quantum phase slip (QPS) junction can act as a superconductor switch when a voltage pulse larger than its critical voltage is applied to it. As a result, a current pulse with an area equal to 2e(or multiples of 2e) flows across the junction, and the junction switches from zero to one in the charge-base logic. For having a proper operation simulation of the QPS junction, it should be overdamped, and the damping factor should be less than one. Physical parameters of the QPS junction, namely, the normal resistance, the kinetic inductance, and the critical voltage, can affect the overdamping condition and switching behavior of the junction, as well as the damping factor. The basic block for designing the QPS logic gates is the charge island. By different and proper connections of the charge islands, basic QPSand, or, andxorlogic gates are designed. Generally, each of these gates has its own circuit and junction parameters for proper operation. In this manuscript, a universal QPS logic gate is proposed that can perform basicand, or, andxorBoolean functions by proper selection of parameters for QPS junctions in the case of each Boolean function. This universal QPS logic gate can simplify the design the complicated QPS logic circuits, since only the parameters of each junction have to be properly selected for achieving the desired Boolean function, and the gate circuit topology remains unchanged.
Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.
Quantum phase‐slips, which are the exact duals of Josephson junctions (JJs), are promising for several applications in classical and quantum superconducting electronic circuits. The experimental testing of the phase‐slip phenomena and identifying these applications has been challenging. In this reported work, the use of a dual to a JJ model to implement a SPICE model of a quantum phase‐slip junction (QPSJ) in JSPICE3, in order to explore possible circuit applications, is demonstrated. A transient analysis model of the device is presented and an example of an I–V curve simulation of the device, along with a simulation of a possible circuit application of the device, are also shown.