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Modelling and Measurement of Reciprocal Quantum Logic Circuits

Henry Luo

Published Jan 1, 2021• 0 citations
Publisher

Abstract

This dissertation presents work on three aspects of Reciprocal Quantum Logic (RQL) circuits: devising accurate inductance models of Nb wires, analyzing, and measuring RQL logic gates, and mitigating the effects of parasitic coupling in RQL circuits. These separate aspects are all important to verify or improve the operating margins of RQL circuits. An inductance model for Nb wire routes based on electromagnetic simulation and measurement of inductance test circuits is described. The inductance test circuits are fabricated in the D-Wave Systems process. The inductance of straight segments, corners, and vias, and the mutual inductance between straight segments are modelled and measured. Measured data from 6 different releases and 8 wafers is presented. Proximity effects and wafer radial effects are discussed. Finally, a 2-material model for Nb wires is introduced and yields a good fit to the measured inductances. An RQL gates testbed chip was designed, fabricated, and tested. This chip was also fabricated in the D-wave Systems process. The measured gates included the buffer Josephson Transmission Line (JTL), delay JTL, and2, and or2 gates. Fifteen different design variations of each of these gates, which varied three inductors in the gate, are analyzed and shown to match well to simulation models. The variation in the upper operating limit or upper margin per design variation was roughly 3.5%, 5%, 7%, and 5% for the buffer JTL, delay JTL, and2, and or2, respectively. Tools were developed to account for and mitigate the effect of parasitic mutual coupling in RQL circuits. A back-annotation RQL tool (BART), to back-annotate parasitic mutual inductance, was developed for the extraction and simulation of small RQL designs. Using this tool on a 2x2 bit memory cell, the back-annotated simulation was able to explain measurements of the different operating regions for different test vectors. A methodology, bias point delta (BPD), for improving signal integrity of RQL circuits is also introduced. This methodology was applied to a 3,274 JJ design and the amount of coupled flux before and after routing improvements are compared. The work in this dissertation describes the development of models and tools that aid in the design of large RQL circuits, and it will serve as the groundwork for future research in RQL and potentially other Single Flux Quantum (SFQ) technologies.

DOI
10.13016/mrpe-2lkk

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This dissertation presents work on three aspects of Reciprocal Quantum Logic (RQL) circuits: devising accurate inductance models of Nb wires, analyzing, and measuring RQL logic gates, and mitigating the effects of parasitic coupling in RQL circuits. These separate aspects are all important to verify or improve the operating margins of RQL circuits. An inductance model for Nb wire routes based on electromagnetic simulation and measurement of inductance test circuits is described. The inductance test circuits are fabricated in the D-Wave Systems process. The inductance of straight segments, corners, and vias, and the mutual inductance between straight segments are modelled and measured. Measured data from 6 different releases and 8 wafers is presented. Proximity effects and wafer radial effects are discussed. Finally, a 2-material model for Nb wires is introduced and yields a good fit to the measured inductances. An RQL gates testbed chip was designed, fabricated, and tested. This chip was also fabricated in the D-wave Systems process. The measured gates included the buffer Josephson Transmission Line (JTL), delay JTL, and2, and or2 gates. Fifteen different design variations of each of these gates, which varied three inductors in the gate, are analyzed and shown to match well to simulation models. The variation in the upper operating limit or upper margin per design variation was roughly 3.5%, 5%, 7%, and 5% for the buffer JTL, delay JTL, and2, and or2, respectively. Tools were developed to account for and mitigate the effect of parasitic mutual coupling in RQL circuits. A back-annotation RQL tool (BART), to back-annotate parasitic mutual inductance, was developed for the extraction and simulation of small RQL designs. Using this tool on a 2x2 bit memory cell, the back-annotated simulation was able to explain measurements of the different operating regions for different test vectors. A methodology, bias point delta (BPD), for improving signal integrity of RQL circuits is also introduced. This methodology was applied to a 3,274 JJ design and the amount of coupled flux before and after routing improvements are compared. The work in this dissertation describes the development of models and tools that aid in the design of large RQL circuits, and it will serve as the groundwork for future research in RQL and potentially other Single Flux Quantum (SFQ) technologies.
Complimentary Medal-Oxide Semiconductor (CMOS) technology is expected to soon reach its fundamental limits of operation. The fundamental speed limit of about 4 GHz has already effectively been sidestepped by parallelization. This increases raw processing power but does nothing to improve power dissipation or latency. One approach for increasing computing performance involves using superconducting digital logic circuits. In this thesis I describe a new kind of superconducting logic, invented by Quentin Herr at Northrop Grumman, which uses reciprocal pairs of quantized single magnetic flux pulses to encode classical bits. In Reciprocal Quantum Logic (RQL) the data is encoded in integer units of the magnetic flux quantum. RQL gates operate without the bias resistors of previous superconducting logic families and dissipate several orders of magnitude less power. I demonstrate the basic operation of key RQL gates (AndOr, AnotB, Set/Reset) and show their self-resetting properties. Together, these gates form a universal logic set and provide memory capabilities. Experiments measuring the bit error rate of the AndOr gate extrapolated a minimum BER of 10−480 and a BER of 10−44 with 30% margins on flux biasing. I describe an analytic timing model for RQL gates which demonstrates the self-correcting timing features. From this model I derive equations for the timing behavior and operating limits. Using this timing model I ran simulations to determine correction factions for more accurate predictions at higher frequencies. Using these results, I also develop Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) models to describe the combinational logic of RQL gates. To test the timing predictions of the timing model, I performed three experiments on Nb/AlOx/Nb circuits at 4.2 K. The first measured the time of output. The second measured the operating margins of the circuit. The third measured the maximum frequency of operation for RQL circuits. Together, these three experiments showed quantitative agreement with the model for the timing output, qualitative agreement with the limits of operation, and a projected speed limit of 50 GHz for the Hypres 4.5 kA/cm2 process. To power RQL circuits I describe a new design for power splitters and combiners which minimize standing waves. I describe a new kind of Wilkinson power splitter which required numerical optimization but proved to be adequate. I experimentally tested two new designs of the power splitter. Both showed less than 10% variation in standing waves between power splitter and combiner, making it adequate for RQL circuits. I also compared these results with the S-parameters of the power network, which also indicated that the design was adequate for RQL circuits. Finally, I tested an 8-bit Kogge-Stone architecture carry-look ahead adder designed using VHDL models. The adder contained 815 Josephson junctions and was fully functional at 6.21 GHz with a latency of 1.25 clock cycles. The adder produced the correct logical output, had a measured optimal operating point within 8% of the optimal simulated operating point, and measured power margins of 1 dB. It operated best at the designed clock amplitude of 0.88 Ic and dissipated 0.570 mW of power.
Superconductor single flux quantum (SFQ) technology is one of the promising candidates for energy-efficient high-performance computing. A new generation of SFQ logics, Reciprocal Quantum Logic (RQL) with no static power dissipation in bias resistors, offers an opportunity to dramatically decrease energy consumption in superconductor processors. Although several low complexity RQL processing units have already been demonstrated, the use of RQL for local storage design has not been explored yet. The objective of this dissertation is to design on-chip local storage structures such as memory, register files, and caches with RQL technology and analyze their energy efficiency, complexity, and performance characteristics. The physical chip design of these RQL storage units is not feasible at this point because both CAD tools for physical VLSI chip design and as well as a target fabrication process are under development at Northrop-Grumman Systems Corp. (Baltimore, MD) and MIT Lincoln Laboratory, respectively. In order to achieve our goal, the layout-aware cell-level design process using VHDL RQL cell library developed at the Ultra High Speed Computing Lab in Stony Brook University has been used. The SBU VHDL RQL cell library specifies the dynamic and stand-by energy consumption, latency, JJ complexity, and approximate sizes of individual cells based on the input received from the JJ-level RQL designers. Clock propagation skew and wire delays are accounted for during circuit simulation. The circuit simulation is done with Mentor Graphics design and verification tools. As a result of the work, key characteristics of the 8.5 GHz multiported RQL storage structures with their capacity in the range of 1-4 kbit have been determined. The average energy consumption of the RQL storage designs is ~3.0-9.5 fJ/bit/operation at room temperature and the cryo-cooling efficiency is 0.1%. The data from this dissertation also reveal the critical issues that need to be considered in the RQL storage design. These will be helpful for further development on superconductor VLSI design. | 124 pages
New superconductor single flux quantum (SFQ) technology, such as Reciprocal Quantum Logic (RQL), is currently considered one of the promising candidates for highperformance energy-efficient computing. This paper presents our work on the design and detailed energy efficiency analysis of three types of 32- and 64-bit RQL multi-ported pipelined local storage structures (13 total), namely 1) random access memory (RAM) and register files, 2) direct-mapped write-through and write-back caches, and 3) first-in-first-out (FIFO) buffers. Our layout-aware cell-level design process uses a VHDL RQL cell library developed at the Ultra High Speed Computing Laboratory at Stony Brook University (SBU). The SBU VHDL RQL cell library specifies the dynamic and standby energy consumption, gate delays, a number of Josephson junctions (JJs) per cell, and approximate sizes of individual cells based on the parameters of the 248 nm 100 μA/μm210 Nb metal layer SFQ fabrication process currently under development at the MIT Lincoln Laboratory. Gate and wire delays as well as clock skew are taken into account during digital circuit simulation done with Mentor Graphics CAD tools. After completing a physical chip layout, the circuit models need to be updated and re-simulated to include the effects of parasitic inductances and actual wire lengths on signal propagation delays. To meet both performance and energy efficiency targets, the RQL storage structures were designed with RQL non-destructive read-out single-bit storage cells. We chose a relatively moderate clock frequency of 8.5 GHz for all storage units to keep their read latencies in the range of 1- 3 cycles. The most complex design in terms of JJs is a tripleported 4 Kbit 64x64-bit register file with 253,918 JJs and its read access latency of 338 ps. The highest energy consumption in terms of energy/operation/bit (~9.5 aJ at 4.2 K) is for a write hit in a 2 Kbit 32-bit wide write-back cache. The average energy consumption of the RQL storage designs varies from ~1.6 aJ/operation/bit for a small 4x32-bit FIFO to 7.3 aJ/operation/bit for the 2 Kbit write-back cache at 4.2 K. Given the cryocooler efficiency of 0.1%, this means the energy consumption of ~1.6-7.3 fJ/operation/bit at room temperature. The physical implementation of the RQL storage units will become feasible upon the development of the target MIT fabrication process and CAD tools for VLSI RQL chip design in 2015-2016.
This paper gives a newfangled dimension to superconducting logic which is the successor of CMOS logic and other superconducting quantum logic. Reciprocal Quantum logic (RQL) is proposed to achieve the less memory capability. RQL is a modified version of Rapid Single Flux Quantum (RSFQ). We designed and analyzed different RQL logic like half adder, full adder, counter, and Carry Save Adder (CSA) and we achieved an increase in clock speed compared to RSFQ logic by 20%. The designs are made of AndOr and AnotB gate operation and analyzed using WRSPICE software.
We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.
ENGLISH ABSTRACT: In this thesis, we cover various methods that improve high-frequency Single Flux Quantum electronics design. Accurately modelling high-frequency effects is vital in high-frequency Single Flux Quantum electronics design. The passive transmission line is, currently, the most inaccurately modelled circuit component. We, therefore, developed a new 2D quasiTransverse-Magnetic method to calculate transmission line properties of superconductor structures. The new method can take into account quasi-particle losses as well as dielectric losses. The frequency response of a passive transmission line with arbitrary length can then readily be obtained from the transmission line properties. The high-frequency response is informative, but a time-domain simulation model is necessary to determine the effect on high-frequency circuit dynamics. Accordingly, we developed the Superconductor Vector Fitting algorithm so that we can take arbitrary superconductor frequency responses and convert them into time-domain simulation models. Complex dynamical behaviour, made more complicated by the new numerical simulation models, currently prohibits designing circuits by only using design equations. Automatic optimization routines are used to adjust circuit parameters to improve fabrication yield. Existing routines suffer from issues ranging from suboptimal circuits to severe performance issues. We developed a new and novel yield optimization algorithm, Distance-To-Failure-Maximization, that can be used to optimize superconductor circuits that are verified u sing time-domain simulations. High-frequency circuits can be sensitive to changes in bias current from parasitics mutual inductances. We developed the fundamental inductance model to model all inductive effects accurately. The fundamental inductance model can also be used to construct design equations which accounts for parasitic effects as well as reduce the number of unknowns in the yield optimization procedure. We use all the above methods in a detailed case study on the design of a JTLT. We take into account attenuation, impedance mismatch, flux mismatch, and resonance during the design of the JTLT circuit. With this, we conclude that the methods we developed have brought significant improvements to high-frequency Single Flux Quantum design.