Many problems in mathematics, statistical mechanics, and computer science are hard to tackle by conventional computational methods, but can be reduced to the combinatorial problem of finding the ground state of the Ising model. However, the computational cost associated with a combinatorial optimization problem increases exponentially with the number of variables. This explains growing research interest towards physical and artificial spin-networks (schematically shown in Fig. 1 (a) ) that evolve according to an Ising Hamiltonian, which provides the combinatorial solution through the ground state observed in the experiment [1] . The implementation of analog autonomous spin-networks is currently considered a highly attractive prospect due to a potentially significant increase in energy efficiency and processing speed.
Many problems in mathematics, statistical mechanics, and computer science are hard to tackle by conventional computational methods, but can be reduced to the combinatorial problem of finding the ground state of the Ising model. However, the computational cost associated with a combinatorial optimization problem increases exponentially with the number of variables. This explains growing research interest towards physical and artificial spin-networks (schematically shown in Fig. 1 (a) ) that evolve according to an Ising Hamiltonian, which provides the combinatorial solution through the ground state observed in the experiment [1] . The implementation of analog autonomous spin-networks is currently considered a highly attractive prospect due to a potentially significant increase in energy efficiency and processing speed.
With the growing demand for efficient computing to tackle complex real-world challenges like combinatorial optimization, both academia and industry are exploring alternative computing paradigms. The Ising machine (IM) is one such approach, solving optimization problems by mapping their cost functions onto the Ising model. In this framework, finding the optimal solution equates to determining the Ising spin configuration corresponding to the ground state of the Ising Hamiltonian. Analog IMs, relying on artificial spins that can take analogue rather than binary values, have shown great potential in reaching this ground at high speeds. Optical implementations, such as the opto-electronic IM developed within our research group, are particularly promising due to their higher bandwidth, energy efficiency, and lower latency compared to electronic IMs. However, scaling remains a challenge for large problems. To overcome this, we propose a novel analog optical IM utilizing a spatial light modulator (SLM). Our design differs from other IMs relying on SLMs by employing analog spin variables instead of binary ones and leveraging gradient descent-based feedback rather than a computer-driven Metropolis–Hastings sampling process. By exploiting the inherent parallelism of light, this SLM-based IM is expected to efficiently handle optimization problems with millions of spins while still maintaining high energy efficiency. At the conference, we will also offer more insight into the performance of these analogue IMs and will delve deeper in the bit resolution required for the different optical components such as the employed SLM. Based on the dynamical evolution of the IM, we will discuss strategies to further improve the problem-solving capacity and speed of these optical IMs.
We show how spatial light modulation allows one to optically compute an Ising Hamiltonian. This enables the use of optical radiation to accelerate algorithms to find the ground state and hence the optimal solution of a combinatorial optimization problem. The phase matrix on a spatial light modulator acts as a lattice of spins whose interaction is ruled by the constrained optical intensity in the far field. Feedback from the detection plane allows the spatial phase distribution to evolve toward the minimum of the selected spin model. Related topics such as annealing, adiabatic evolution, the XY model, and decomposition methods are reviewed.
This research is concerned with an annealing processor for efficiently solving a combinatorial optimization problem.\nIn order to realize a smart society, optimization of people and thingssuch as transportation networks, power networks, human resource allocationand routes is indispensable. Many of these problems are called combinatorial optimization problems and are known as very important problems in modern society. However, it is known that the combinatorial optimization problem is NP-hard and it is difficult to efficiently solve it with a conventional Neumann computer.\nIn recent years, the miniaturization of the process of manufacturing computer chips is approaching the physical limit. Therefore, especially in the solution by the full search, the improvement in speed due to the calculation speed of the computer cannot be expected. From such a background, dedicated hardware capable of solving a combination optimization problem at high speed and with low power consumption has been attracting attention.\nThe annealing processor is a general-purpose combination optimization solver that utilizes the property that the ground state of the optimization problem expressed by using the Ising model and the optimal solution of the combination optimization problem match. The Ising model is a ferromagnetic model in statistical physics expressed by spins having an upward and downward state, spin-spin interactions occurring between the spins, and an external magnetic field acting on each spin. The Ising model can express a combinatorial optimization problem by expressing a control target and a cost using these parameters. The annealing processor updates the spin state while slowly lowering the temperature parameters based on simulated annealing,which is an optimization method learned from natural phenomena generally called annealing. Eventually, the spin will reach the ground state with a high probability and obtain the optimal solution.\nAnnealing processors are classified into two types, the nearest neighbor type and the fully connected type, depending on the shape of the Ising model simulated on the hardware. In the nearest neighbor type, the coupling between spins is limited to only between adjacent spins, and in the full coupling type, coupling exists between arbitrary spins. The nearest neighbor type realizes high parallel processing by reducing the data spin required by simulated annealing by reducing the proximity spin. In addition, since data transfer is limited to adjacent spins, the scalability is high. However, since the spin-to-spin interaction is sparse, there is a problem that the class of combinatorial optimization problems that can be dealt with is limited, or that the problem requires deformation processing to match the Ising model of hardware. The fully connected type can solve any class of problems as long as the number of spins permits, however it requires connections between arbitrary spins.Therefore, scalability is low. Because there there is a dependency on all spins,the number of spins that can be updated at one time is always limited to only one regardless of the total number of spins. Therefore, it takes time to converge to the ground state.\nIn this research, we propose a method of increasing the number of spins for this annealing processor by using (1) a spatially-expanded time-division processing mechanism architecture based on a loosely-coupled type, (2) An algorithm for applying a fully coupled Ising network to a more complex Ising network using the nearest neighbor Ising network and an annealing method that can be updated in parallel, (3)We conducted a study on the architecture of a fully coupled annealing processor for parallel updating annealing.\nAs described above, the research described in this paper contributes to the improvement of the efficiency of the annealing processor for solving the large-scale combinatorial optimization problem from both the fundamental algorithm and the hardware architecture. I hope that this research will solve the combinatorial optimization problem that is expected to increase in demand in the future and contribute to the development of human society.
Unconventional computers based on superconducting qubits [1] and analog/digital hardware accelerators [2]–[5] have been developed and solved hard combinatorial optimization problems (COPs) with higher efficiency than classical computers by integrating the Ising models in hardware and observing their natural convergence behavior towards the lower Ising Hamiltonian (or energy). Ouantum annealer based on superconducting qubits [1] has demonstrated its capability of finding solutions to COPs using the quantum tunneling effect. However, the quantum computer requires operating at ultra-low temperatures (15-20mK), consumes excessive power (>10kW), and is not scalable yet to solve real-world problems. Recently, ASIC hardware accelerators [2]–[5] using low-cost CMOS technologies have implemented the Ising model by integrating many physical spins (i.e., computing units of the Ising model) to accelerate the finding of solutions to hard COPs. The hardware accelerators, so-called Ising machines, solved hard COPs much faster than classical computers and consumed several orders of magnitude lower energy. Nevertheless, they still have to overcome the fundamental scalability issues for solving large-scale COPs in the real world. The performance of existing discrete-time Ising machines has been limited by the exponentially increasing number of operation cycles when the problem size increases for the large-scale COPs. in addition, prior works have not been able to integrate massive random number generators (RNG), the essential building blocks of the Ising machines for finding better solutions, that could occupy a significant hardware footprint. Prior works have implemented them off-chip, or a few have been integrated on-chip and shared by many spins. This paper proposes a novel continuous-time analog Ising machine based on coupled inveiter chain circuits to address the scalability issues of the existing discrete-time Ising machines. Besides the benefits of the continuous-time operation, which significantly lowers the computing energy and latency, we introduce an equalization method for finding better solutions without RNGs.