A quest for the optimal design of π-coupled Josephson junctions

Tomohiro Kamiya, Shozo TANIGUCHI, Kyosuke Sano +2 more

Yuki Yamanashi, Sotaro Nakaishi, Naoki Takeuchi +1 more

Yuki Yamanashi, Sotaro Nakaishi, Nobuyuki Yoshikawa

We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.

Tomoya Ogawa, Katsuhiko Miyamoto, Daisuke Suzuki +2 more

Eva Dupont-Ferrier, Sergey P. Gladchenko, L. B. Ioffe +1 more

Yuki Yamanashi, Sotaro Nakaishi, Akira Sugiyama +2 more

A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π -shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π -shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π -shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and π -shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0- π Josephson junctions.