Quantum computing is an emerging technology that combines the principles of both computer science and quantum mechanics to solve computationally challenging problems significantly faster than the current classical computers. In this thesis, a proof of concept to generate hardware-executable quantum circuits for Noisy Intermediate-Scale Quantum (NISQ) devices that follow the paradigm of approximate computing is presented. We adopt a multi-level optimization approach and consider the placement of native quantum gates that can be physically implemented on one of the existing quantum systems (IBM, Rigetti) as a circuit topology optimization problem and the adjustment of parameters of these native quantum gates as a continuous design optimization problem. The outer topology problem is solved with the aid of a genetic algorithm, whereas the gradient-descent method is used for the inner design optimization. Our approach starts from the reference circuit and transforms it into an executable circuit with tunable parameters by replacing the high-level quantum operations with a set of approximate decompositions, e.g., single qubit rotation quantum gates or a combination of single qubit rotation gates (matrix multiplication). Later, the inner design optimization ensures that the circuit created is tuned to be executed to achieve an expectation value close to that of the reference circuit. This is complemented by compiler-based optimizations to further reduce or aggregate the quantum gates of the optimized circuit. This three-step pipeline is embedded into an outer genetic algorithm framework that inspects many different circuit designs (the approximate-decomposition replacements are by no means unique) and returns a set of unique approximate quantum circuits that can be executed on hardware. We have tested our circuit generation approach for superconducting quantum systems such as IBM and Rigetti hardware for many different benchmark circuits such as Quantum Fourier Transform, Toffoli, quantum adder, multi-controlled operations and three oracle-based algorithms, namely, Grover's search algorithm, Deutsch and Bernstein-Vazirani algorithm. In nearly all cases, our approach outperforms the quantum compiler frameworks by IBM and Rigetti even on their highest optimization level and produces significantly smaller circuits, up to 2x reduction in the number of gates. In addition, the circuits generated using the proposed approach provide better (a) performance (on average, improved by 24.25%) and (b) reliability (on average, improved by 23.50%) compared to the IBM generated circuits when executed on the ibmq_5_yorktown physical quantum device.
Quantum computing is an emerging technology that combines the principles of both computer science and quantum mechanics to solve computationally challenging problems significantly faster than the current classical computers. In this thesis, a proof of concept to generate hardware-executable quantum circuits for Noisy Intermediate-Scale Quantum (NISQ) devices that follow the paradigm of approximate computing is presented. We adopt a multi-level optimization approach and consider the placement of native quantum gates that can be physically implemented on one of the existing quantum systems (IBM, Rigetti) as a circuit topology optimization problem and the adjustment of parameters of these native quantum gates as a continuous design optimization problem. The outer topology problem is solved with the aid of a genetic algorithm, whereas the gradient-descent method is used for the inner design optimization. Our approach starts from the reference circuit and transforms it into an executable circuit with tunable parameters by replacing the high-level quantum operations with a set of approximate decompositions, e.g., single qubit rotation quantum gates or a combination of single qubit rotation gates (matrix multiplication). Later, the inner design optimization ensures that the circuit created is tuned to be executed to achieve an expectation value close to that of the reference circuit. This is complemented by compiler-based optimizations to further reduce or aggregate the quantum gates of the optimized circuit. This three-step pipeline is embedded into an outer genetic algorithm framework that inspects many different circuit designs (the approximate-decomposition replacements are by no means unique) and returns a set of unique approximate quantum circuits that can be executed on hardware. We have tested our circuit generation approach for superconducting quantum systems such as IBM and Rigetti hardware for many different benchmark circuits such as Quantum Fourier Transform, Toffoli, quantum adder, multi-controlled operations and three oracle-based algorithms, namely, Grover's search algorithm, Deutsch and Bernstein-Vazirani algorithm. In nearly all cases, our approach outperforms the quantum compiler frameworks by IBM and Rigetti even on their highest optimization level and produces significantly smaller circuits, up to 2x reduction in the number of gates. In addition, the circuits generated using the proposed approach provide better (a) performance (on average, improved by 24.25%) and (b) reliability (on average, improved by 23.50%) compared to the IBM generated circuits when executed on the ibmq_5_yorktown physical quantum device.
Quantum computing emerges as a promising direction for high-performance computing in the post-Moore era. Leveraging quantum mechanical properties, quantum devices can theoretically provide significant speedup over classical computers in certain problem domains. Quantum algorithms are typically expressed as quantum circuits composed of quantum gates, or as unitary matrices. Execution of quantum algorithms on physical devices requires translation to machine-compatible circuits -- a process referred to as quantum compilation or synthesis. Quantum synthesis is a challenging problem. Physical quantum devices support a limited number of native basis gates, requiring synthesized circuits to be composed of only these gates. Moreover, quantum devices typically have specific qubit topologies, which constrain how and where gates can be applied. Consequently, logical qubits in input circuits and unitaries may need to be mapped to and routed between physical qubits on the device. Current Noisy Intermediate-Scale Quantum (NISQ) devices present additional constraints, through their gate errors and high susceptibility to noise. NISQ devices are vulnerable to errors during gate application and their short decoherence times leads to qubits rapidly succumbing to accumulated noise and possibly corrupting computations. Therefore, circuits synthesized for NISQ devices need to have a low number of gates to reduce gate errors, and short execution times to avoid qubit decoherence. The problem of synthesizing device-compatible quantum circuits, while optimizing for low gate count and short execution times, can be shown to be computationally intractable using analytical methods. Therefore, interest has grown towards heuristics-based compilation techniques, which are able to produce approximations of the desired algorithm to a required degree of precision. In this work, we investigate using Genetic Algorithms (GAs) -- a proven gradient-free optimization technique based on natural selection -- for circuit synthesis. In particular, we formulate the quantum synthesis problem as a multi-objective optimization (MOO) problem, with the objectives of minimizing the approximation error, number of multi-qubit gates, and circuit depth. We also employ fuzzy logic for runtime parameter adaptation of GA to enhance search efficiency and solution quality of our proposed quantum synthesis method.
Quantum algorithms will likely play a key role in future high-performance-computing (HPC) environments. These algorithms are typically expressed as quantum circuits composed of arbitrary gates or as unitary matrices. Executing these on physical devices, however, requires translation to device-compatible circuits, in a process called quantum compilation or circuit synthesis, since these devices support a limited number of native gates. Moreover, these devices typically have specific qubit topologies, which constrain how and where gates can be applied. Consequently, logical qubits in input circuits and unitaries may need to be mapped to and routed between physical qubits. Furthermore, current Noisy Intermediate-Scale Quantum (NISQ) devices present additional constraints. They are vulnerable to errors during gate application and their short decoherence times lead to qubits rapidly succumbing to accumulated noise and possibly corrupting computations. Therefore, circuits synthesized for NISQ devices need to minimize gates and execution times. The problem of synthesizing device-compatible circuits, while optimizing for low gate count and short execution times, can be shown to be computationally intractable using analytical methods. Therefore, interest has grown towards heuristics-based synthesis techniques, which are able to produce approximations of the desired algorithm, while optimizing depth and gate-count. In this work, we investigate using genetic algorithms (GA)—a proven gradient-free optimization technique based on natural selection—for circuit synthesis. In particular, we formulate the quantum synthesis problem as a multi-objective optimization (MOO) problem, with the objectives of minimizing the approximation error, number of multi-qubit gates, and circuit depth. We also employ fuzzy logic for runtime parameter adaptation of GA to enhance search efficiency and solution quality in our proposed method.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Rapid advancement in the domain of quantum technologies has opened up researchers to the real possibility of experimenting with quantum circuits and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise poses a challenge in the smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit count with the recent emphasis on topology-aware (nearest-neighbor compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks show that the fidelity of the circuit can be improved up to 3.37X with an average improvement of 1.87X.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale.
In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
Gate-based quantum algorithms are typically implemented by circuits consisting of many single-qubit and multi-qubit gates operating on a quantum input state, followed by measurements of the output state. For certain quantum subroutines, such as initial state preparation and quantum Fourier transforms, explicit decompositions of the circuit in terms of single-qubit and two-qubit maximally entangling gates may exist. However, they often lead to large-depth circuits that are challenging for noisy intermediate-scale quantum (NISQ) hardware. Additionally, exact decompositions might only exist for some modular quantum circuits. Therefore, it is essential to find gate combinations that approximate these circuits to high fidelity with potentially low depth. Gradient-based optimization has been used to find such approximate decompositions. Still, these traditional optimizers often run into problems of slow convergence requiring many iterations, and performing poorly in the presence of noise, a factor that is especially relevant for NISQ hardware. Here we present iteratively preconditioned gradient descent (IPG) for optimizing quantum circuits and demonstrate performance speedups for state preparation and implementation of quantum algorithmic subroutines. IPG is a noise-resilient, higher-order algorithm that has shown promising gains in convergence speed for classical optimizations, converging locally at a linear rate for convex problems and superlinearly when the solution is unique. Specifically, we show an improvement in fidelity by a factor of 104for preparing a 4-qubit W state and a maximally entangled 5-qubit GHZ state with compared to other commonly used classical optimizers tuning the same ansatz. Such faster convergence with promise for noise-resilience could provide advantages for quantum algorithms on NISQ hardware, especially since the cost of running each iteration on a quantum computer is substantially higher than the classical optimizer step.