In the midst of the NISQ era of quantum computers, the challenges are gravitating to encompass both architecting and full-stack engineering aspects, which are inherently algorithm-driven, so that there starts to be a convergence of bottom-up and top down design approaches, what we coin as the Quantum Architecting (QuArch) era. In face of many-fold diverse design proposals, in this paper it is postulated and proposed to apply the so-called Design Space Exploration (DSE) to the full vertical stack of quantum systems as an instrumental methodology to address such design diversity challenge. This structured design means, based upon composing a multidimensional input design space together with compressing the set of output performance metrics into an optimization-oriented overall figure of merit, provides a framework and method for optimization, for performance comparison. It yields as well a way to discriminate among alternative techniques at all layers and across layers, eventually as a structured and comprehensive design-oriented formal framework to address the quantum system design and evaluation complexity. The paper concludes by illustrating instances of this methodology in optimizing and comparing mapping techniques to address the resource-constrained current NISQ quantum chips, and to carry out a quantitative gap analysis of scalability trends aiming manycore distributed quantum architectures.
In the midst of the NISQ era of quantum computers, the challenges are gravitating to encompass both architecting and full-stack engineering aspects, which are inherently algorithm-driven, so that there starts to be a convergence of bottom-up and top down design approaches, what we coin as the Quantum Architecting (QuArch) era. In face of many-fold diverse design proposals, in this paper it is postulated and proposed to apply the so-called Design Space Exploration (DSE) to the full vertical stack of quantum systems as an instrumental methodology to address such design diversity challenge. This structured design means, based upon composing a multidimensional input design space together with compressing the set of output performance metrics into an optimization-oriented overall figure of merit, provides a framework and method for optimization, for performance comparison. It yields as well a way to discriminate among alternative techniques at all layers and across layers, eventually as a structured and comprehensive design-oriented formal framework to address the quantum system design and evaluation complexity. The paper concludes by illustrating instances of this methodology in optimizing and comparing mapping techniques to address the resource-constrained current NISQ quantum chips, and to carry out a quantitative gap analysis of scalability trends aiming manycore distributed quantum architectures.
Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
The advances in quantum hardware with functional quantum processors integrating tens of noisy qubits, together with the availability of near-term quantum algorithms have allowed the development of the so-called full-stacks that bridge quantum applications with quantum devices. In this talk, we will provide an overview of the different layers of the quantum computing full-stack, with emphasis on the software ones that include the compilation of quantum algorithms. We will then discuss the need for optimal physical-aware and algorithm-driven compilation techniques in the midst of the NISQ (Noisy Intermediate-scale quantum) era. We will also focus on key principles for architecting quantum computers such as codesign, optimization and benchmarking and illustrate how the use of structured design space exploration methodologies could help towards the development of a cross-layer codesign framework for full-stack quantum computing systems. Finally, we will talk about the scalability of quantum computing systems, which is one of the main challenges the quantum computing community is currently facing.
The progress in developing quantum hardware with functional quantum processors integrating tens of noisy qubits, together with the availability of near-term quantum algorithms has led to the release of the first quantum computers. These quantum computing systems already integrate different software and hardware components of the so-called “full-stack”, bridging quantum applications to quantum devices. In this paper, we will provide an overview on current full-stack quantum computing systems. We will emphasize the need for tight co-design among adjacent layers as well as vertical cross-layer design to extract the most from noisy intermediate-scale quantum (NISQ) processors which are both error-prone and severely constrained in resources. As an example of co-design, we will focus on the development of hardware-aware and algorithm-driven compilation techniques.
Design, simulation, analysis and verification methodologies are crucial for developing electronic circuits and systems at large. Whereas long-standing EDA software is used in the semiconductor technology, there is no counterpart for quantum computing systems yet. Although the quantum computing community started utilizing and adapting some of the already existing EDA tools, for instance, to design quantum processors and control electronics for driving the qubits, or even to solve some quantum computing design tasks, they do not fully use the expertise gained over the last decades in the field of design automation. Current intermediate-scale quantum computers have been designed in an ‘adhoc’ manner with heterogeneous methods and tools. As we are entering the large-scale era, it is timely and key to further adopt EDA methodologies and software for quantum computing. In this paper, we provide an overview on how full-stack quantum computing systems are being implemented nowadays and discuss which the main challenges are for transitioning from this current scenario to a comprehensive framework encompassing full automated system-wide architecting, design, simulation, verification, and test.
Being a very promising technology, with impressive advances in the recent years, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Although continued progress in the fabrication and control of qubits is required, quantum computing scalability will depend as well on a comprehensive architectural design considering a distributed multi-core approach as an alternative to the traditional monolithic version, hence including a communications perspective. However, this goes beyond introducing mere interconnects. Rather, it implies consolidating the full communications stack in the quantum computer structure. In this paper, we propose a double full-stack architecture encompassing quantum computation and quantum communications, which we use to address the monolithic versus distributed question with a structured design methodology. For that, we revisit the different quantum computing layers to capture and model their essence by highlighting the open design variables and performance metrics. Using behavioral models and actual measurements from existing quantum computers, the results of simulations suggest that multicore architectures may effectively unleash the full quantum computer potential.
Quantum computers have emerged as an alternative computer paradigm that will allow to solve some complex problems of large numbers that are not tractable for classical computers, e.g. factorization. Quantum computers also have the ability to simulate quantum mechanics in a real and direct way. The development of quantum computers faces many unique obstacles. In recent years, various quantum computer prototypes have been created by com- panies such as Google and IBM, on which we can run some quantum algorithms. But these prototypes are far from the quantum computers we envision and can function like today?s classical computers. It is said that we are in the time of Noisy Intermediate-Scale Quantum (NISQ) computers. This means that current quantum computers are very noisy and their size is very small compared to classical comput- ers. The challenge with small, noisy quantum devices running quantum algorithms is that due to the hardware limitations they face which must be respected, quantum algorithm needs to be modified before their execution on quantum devices. To solve this problem in quantum computers, a mapping process is needed, which is part of the compilation step that modifies the quantum algorithms to take into account all the limitations of the targeted quantum device. After mapping process, the resulting quantum circuit usually has a higher number of gates and (execution time) latency, decreasing the algorithm?s reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quan- tum processor and different in methodology, approach and features. In addition, they are usually only compared in terms of added gates (gate overhead) or added circuit execution time (latency overhead). No thorough comparative analysis of the different mapping solutions performance and features has been performed so far. In this thesis, we apply structured Design Space Exploration to the mapping of quantum circuits. By doing so, we will be able to have a deeper understanding of this process, make a thorough comparison of the mapper approaches and even develop optimized solutions for given applications and quantum devices. Moreover, we apply Design Space Exploration to the generation of quantum algorithms used as benchmarks and start to explore profiling them in a structured approach.