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IEICE Technical Report; IEICE Tech. Rep.

Design of High Timing Resolution SFQ Signal Processing Circuit for SNSPD using 10kA/cm^2 Nb Process

Yuichi Hasegawa, Shohei Sasaki, Masato Naruse, Tohru Taino, Lin Kang, Jian Chen, Peiheng Wu, Hiroaki Myoren

Published Aug 26, 2020• 0 citations
OpenAlex

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10kA/cm^2プロセスを用いた2-bitビットスライス・アダーの設計と評価

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Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa +4 more

Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.

IEICE Transactions on Electronics•Jan 1, 2014•13 citations
A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.