aqora

Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes

Yongmei Dai, Ning Chen, Zhiyuan Yan

In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achievefasterconvergenceandbettererrorperformancethan the sum-product (SP) decoding algorithm, but also needlessmemoryin implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achievessignificantlyhigherthroughputand requireslessmemorythan previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achievefasterconvergenceandbettererrorperformancethan the sum-product (SP) decoding algorithm, but also needlessmemoryin implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achievessignificantlyhigherthroughputand requireslessmemorythan previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.

IEEE Transactions on Circuits and Systems I Regular PapersOct 1, 200842 citations

Design and FPGA Implementation of a Quasi-Cyclic LDPC Decoder

Honglin Zhao, Haiyue Zhang

Lecture notes in electrical engineeringJun 6, 20181 citation

Implementation of Cyclic-Layered QC-LDPC decoder on FPGA

Jianfeng Fan

Jan 1, 20130 citations

Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

Kiran Gunnam, Gwan Choi, Weihuang Wang +2 more

The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi- cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi- cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.

Asilomar Conference on Signals, Systems and Computers (ACSSC)Jan 1, 200626 citations

Design and Efficient Hardware Implementation Schemes for Non-Quasi-Cyclic LDPC Codes

Baihong, Lin -, Yukui +5 more

Tsinghua Science & TechnologyJan 1, 20170 citations

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

Zhongfeng Wang, Zhiqiang Cui

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterationsThis paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsJan 1, 2007155 citations

A Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC codes

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