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IEEE Transactions on Circuits and Systems I Regular Papers

Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes

Yongmei Dai, Ning Chen, Zhiyuan Yan

Published Oct 1, 2008• 42 citations
Publisher

Abstract

In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achievefasterconvergenceandbettererrorperformancethan the sum-product (SP) decoding algorithm, but also needlessmemoryin implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achievessignificantlyhigherthroughputand requireslessmemorythan previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.

DOI
10.1109/tcsi.2008.922024

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In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achievefasterconvergenceandbettererrorperformancethan the sum-product (SP) decoding algorithm, but also needlessmemoryin implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achievessignificantlyhigherthroughputand requireslessmemorythan previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.
In this paper, we first propose a parallel turbo-sum-product (PTSP) decoding algorithm for quasi-cyclic (QC) low-density parity-check codes, and show that our proposed algorithm achieves better error performance and faster convergence than the sum-product (SP) or overlapped SP (OSP) algorithm. Based on our PTSP algorithm, we then propose a partly parallel decoder architecture, which requires smaller memory size, less memory access and power consumption, and simpler control than decoder architectures based on the OSP algorithm.
We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.
In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization efficiency, partly parallel parity check and pipelined access to memory are utilized. Impacts of different node update algorithms and quantization schemes are studied. FPGA implementation of our proposed architectures for a (1536.768) (3.6)-regular QC LDPC code can achieve an estimated 61 Mbps decoding throughput at SNR=4.5dB. Finally, noncoherent OSP decoder, which does not always satisfy the data dependency constraints, is proposed to ensure that the maximum throughput gain 2 of the OSP decoding is achieved for all QC LDPC codes
In this paper, we first propose a turbo-sum-product (TSP) decoding algorithm for quasi-cyclic (QC) low-density parity-check (LDPC) codes and show that our proposed algorithm not only achieves faster convergence and better error performances than the sum-product (SP) algorithm, but also needs less memory in implementation. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and achieves a better tradeoff between sub-iterations and convergence rate, leading to a higher throughput. We also propose a shuffled-sum-product (SSP) decoding algorithm, which is the dual of the TSP algorithm.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
This paper studied the QC-LDPC(quasi-cyclic low density parity check) codes and min-sum decoding algorithm,and designed a proper ununiform decoding scheme for quantization.According to the structure of parity check matrix of QC-LDPC code,a decoder architecture was designed,with its components and function discussed in detail.According the decoding algorithm and quantization scheme,simulated error correcting performance was made.A QC-LDPC decoder was implemented in Xilinx XC3S2000 FPGA(field programmable gate array),whose codeword length is 9 216 and code rate 1/2.FPGA implementation results show that 30% memory can be reduced compared to the traditional designs,achieving better tradeoff between performance and complexity.