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IEEE Transactions on Communications

Memory-efficient and high-throughput decoding of quasi-cyclic LDPC codes

Yongmei Dai, Zhiyuan Yan, Ning Chen

Published Apr 1, 2009• 4 citations
Publisher

Abstract

We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.

DOI
10.1109/tcomm.2009.04.060349

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We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.
In this paper, we first propose a turbo-sum-product (TSP) decoding algorithm for quasi-cyclic (QC) low-density parity-check (LDPC) codes and show that our proposed algorithm not only achieves faster convergence and better error performances than the sum-product (SP) algorithm, but also needs less memory in implementation. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and achieves a better tradeoff between sub-iterations and convergence rate, leading to a higher throughput. We also propose a shuffled-sum-product (SSP) decoding algorithm, which is the dual of the TSP algorithm.
In this paper, we first propose parallel turbo-sum-product (PTSP) and turbo-shuffled-sum-product (TSSP) decoding algorithms for partly parallel decoder architectures of quasi-cyclic (QC) low-density parity-check (LDPC) codes. Our proposed algorithms not only achievefasterconvergenceandbettererrorperformancethan the sum-product (SP) decoding algorithm, but also needlessmemoryin implementation. Then we propose a partly parallel decoder architecture based on our PTSP algorithm and implement it using FPGA. Our PTSP decoder architecture achievessignificantlyhigherthroughputand requireslessmemorythan previously proposed decoder architectures with the same FPGA and LDPC code. Finally, to further reduce the memory requirement, we also propose a partly parallel decoder architecture based on our TSSP algorithm.
In this paper, we first propose a parallel turbo-sum-product (PTSP) decoding algorithm for quasi-cyclic (QC) low-density parity-check codes, and show that our proposed algorithm achieves better error performance and faster convergence than the sum-product (SP) or overlapped SP (OSP) algorithm. Based on our PTSP algorithm, we then propose a partly parallel decoder architecture, which requires smaller memory size, less memory access and power consumption, and simpler control than decoder architectures based on the OSP algorithm.
In this brief, a shuffled schedule (SS) of the min-max decoding algorithm is proposed for nonbinary low-density parity-check (LDPC) codes. To increase the throughput and reduce the memory requirement, a modified SS (MSS) with much simpler check node processing is also proposed, based on a new shuffled merge algorithm. Numerical simulations for three LDPC codes with different lengths and rates over GF(32) show: 1) both SS and MSS converge faster and have slightly better error performance than the flooding schedule, and 2) the degradation of the MSS in error performance as well as convergence rate is negligible. Finally, an efficient decoder architecture based on the MSS is proposed for quasi-cyclic LDPC codes. The proposed decoder architecture further enhances the decoding throughput with improved check and variable node processing units. The implementation results of an (837, 726) LDPC decoder over GF(32) demonstrate that the proposed architecture outperforms those in previous works.
In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization efficiency, partly parallel parity check and pipelined access to memory are utilized. Impacts of different node update algorithms and quantization schemes are studied. FPGA implementation of our proposed architectures for a (1536.768) (3.6)-regular QC LDPC code can achieve an estimated 61 Mbps decoding throughput at SNR=4.5dB. Finally, noncoherent OSP decoder, which does not always satisfy the data dependency constraints, is proposed to ensure that the maximum throughput gain 2 of the OSP decoding is achieved for all QC LDPC codes
In this paper, we propose a turbo decoding message-passing (TDMP) algorithm to decode regular and irregular low-density parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase message-passing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations). Second, the corresponding decoder architecture has a significantly reduced memory requirement that amounts to a savings of (75 + 25n//spl Sigma/ node-degrees)% > 75% for code-length n. A decoder architecture featuring the TDNW algorithm is also presented. Furthermore, we propose a new structure on the parity-check matrix of an LDPC code based on permutation matrices aimed at reducing interconnect complexity and improving decoding throughput. In addition, we construct a wide range of LDPC codes based on Ramanujan graphs which possess this structure.