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Tsinghua Science & Technology

Design and Efficient Hardware Implementation Schemes for Non-Quasi-Cyclic LDPC Codes

Baihong, Lin -, Yukui, Pei Pei, Liuguo, Yin Yin, Jianhua, LU LU

Published Jan 1, 2017• 0 citations
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Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

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The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.

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Construction of the cyclic block-type LDPC codes for low complexity hardware implementation

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In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.

IEEE International Conference on Electronics, Circuits and Systems (ICECS)•Aug 1, 2008•2 citations
The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In addition, layered decoding is applied, and the hardware units are optimized to reduce the latency and area. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity analysis, the proposed decoder with 5 iterations for a (837,726) code over GF(25) can easily achieve 60 Mbps throughput on ASIC devices. It is 40% more efficient than prior designs.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.