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A Noise-Aware Qubit Mapping Algorithm Evaluated via Qubit Interaction-Graph Criteria

Matthew Steinberg, Sebastian Feld, Carmen G. Almudéver, Michael Marthaler, Jan-Michael Reiner

Published Mar 29, 2021• 1 citation
OpenAlex

Abstract

The qubit-mapping problem aims to assign qubits from a quantum circuit to a realistic NISQ device in order to maximize limited resources. Many algorithmic solutions for the qubit-mapping problem have been introduced, but much work remains in order to evaluate the effectiveness of a qubit-mapping algorithm with respect to mapping a circuit to devices while taking into account the noise characteristics of the device. In this work, we make progress on this question. Firstly, we introduce a noise-aware heuristic mapping algorithm which fares well when compared to brute-force and trivial mapping solutions for several benchmarks. This comparison serves to provide effective upper and lower bounds for our heuristic mapper in terms of an algorithm's success rate. Subsequently, we analyze how the performance of the mapping algorithm is affected by the characteristics of the interaction graph, which represents the interactions of qubits in a quantum circuit. We observe that as interaction-graph edges are added to benchmarks in either depth-first or breadth-first fashion, our heuristic algorithm's calculated success rate varies significantly, implying that both the amount of interaction-graph vertex degree and the distribution of edges in a quantum circuit's interaction graph play a significant role in the calculated success rate when our greedy heuristic maps to a quantum device's coupling graph. Lastly, we discovered that our heuristic algorithm provides substantial benefits over the trivial solution when mapping quantum circuits to QPUs, provided that less than approximately 75\% of the QPU is occupied. Lastly, as the size of the quantum processor in our simulation grows, so do the purported benefits from utilizing our heuristic mapper. This work takes the first steps towards the characterization of quantum algorithms with respect to efficient qubit-mapping solutions in NISQ-era devices.

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To run a quantum program in the real device, the compiler maps the logical qubits to physical qubits. This is the most crucial step of compiling a quantum circuit. Because the fidelity of a quantum circuit depends heavily on this mapping process. However, this qubit mapping problem is NP-complete. Therefore, we should resort to heuristics to find high-fidelity mappings. In this paper, we focused on finding efficient heuristic techniques to incorporate real-time error feedback and device connectivity information in order to achieve high fidelity mapping of the quantum circuits. We performed extensive analysis and experimental study based on two baseline algorithms. We performed our experimentation on various combinations of different error rates and heuristic techniques. Consequently, we designed very elegant techniques to consider both all types of real-time error feedback and connectivity information. We showed that our best heuristic approach performs \textbf{1.62x} ( on average) better than one baseline and \textbf{1.934x} ( on average ) better than the other baseline on random benchmarks. Finally, we compared our best heuristic ( CAES ) with the state-of-the-art heuristic-based mapping algorithm on representative benchmarks. We found that CAES performed \textbf{1.7x} ( on average ) better than the state of the art in terms of success rate.

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The qubit-mapping problem aims to assign qubits from a quantum circuit to a realistic NISQ device in order to maximize limited resources. Many algorithmic solutions for the qubit-mapping problem have been introduced, but much work remains in order to evaluate the effectiveness of a qubit-mapping algorithm with respect to mapping a circuit to devices while taking into account the noise characteristics of the device. In this work, we make progress on this question. Firstly, we introduce a noise-aware heuristic mapping algorithm which fares well when compared to brute-force and trivial mapping solutions for several benchmarks. This comparison serves to provide effective upper and lower bounds for our heuristic mapper in terms of an algorithm's success rate. Subsequently, we analyze how the performance of the mapping algorithm is affected by the characteristics of the interaction graph, which represents the interactions of qubits in a quantum circuit. We observe that as interaction-graph edges are added to benchmarks in either depth-first or breadth-first fashion, our heuristic algorithm's calculated success rate varies significantly, implying that both the amount of interaction-graph vertex degree and the distribution of edges in a quantum circuit's interaction graph play a significant role in the calculated success rate when our greedy heuristic maps to a quantum device's coupling graph. Lastly, we discovered that our heuristic algorithm provides substantial benefits over the trivial solution when mapping quantum circuits to QPUs, provided that less than approximately 75% of the QPU is occupied. Lastly, as the size of the quantum processor in our simulation grows, so do the purported benefits from utilizing our heuristic mapper. This work takes the first steps towards the characterization of quantum algorithms with respect to efficient qubit-mapping solutions in NISQ-era devices.
The qubit-mapping problem aims to assign and route qubits of a quantum circuit onto an noisy intermediate-scale quantum (NISQ) device in an optimized fashion, with respect to some cost function. Finding an optimal solution to this problem is known to scale exponentially in computational complexity; as such, it is imperative to investigate scalable qubit-mapping solutions for NISQ computation. In this work, a noise-aware heuristic qubit-assignment algorithm (which assigns initial placements for qubits in a quantum algorithm to qubits on an NISQ device, but does not route qubits during the quantum algorithm’s execution) is presented and compared against the optimalbrute-forcesolution, as well as a trivial qubit assignment, with the aim to quantify the performance of our heuristic qubit-assignment algorithm. We find that for small, connected-graph algorithms, our heuristic-assignment algorithm faithfully lies in between the effective upper and lower bounds given by the brute-force and trivial qubit-assignment algorithms. Additionally, we find that the topological-graph properties of quantum algorithms with over six qubits play an important role in our heuristic qubit-assignment algorithm’s performance on NISQ devices. Finally, we investigate the scaling properties of our heuristic algorithm for quantum processors with up to 100 qubits; here, the algorithm was found to be scalable for quantum-algorithms that admit path-like graphs. Our findings show that as the size of the quantum processor in our simulation grows, so do the benefits from utilizing the heuristic qubit-assignment algorithm, under particular constraints for our heuristic algorithm. This work, thus, characterizes the performance of a heuristic qubit-assignment algorithm with respect to the topological-graph and scaling properties of a quantum algorithm that one may wish to run on a given NISQ device.
Quantum circuit compilation and qubit mapping represent critical challenges in noisy intermediate-scale quantum (NISQ) devices due to limited qubit connectivity and the presence of hardware noise. Conventional heuristic mapping methods often generate suboptimal solutions under realistic noisy execution conditions. This paper proposes a hybrid learning-guided framework that integrates a quantum genetic algorithm (QGA) with a quantum support vector machine (QSVM) for noise-aware qubit mapping optimization in NISQ systems. In the proposed framework, QGA generates diverse candidate mappings, while QSVM-based supervised ranking identifies high-quality mappings using structural and execution-related features. To evaluate the effectiveness of the proposed mapping selection strategy, a QROC/Q-AUC-based evaluation mechanism is introduced to quantify the decision reliability and ranking capability of the mapping selection process under noisy quantum execution conditions. Extensive experiments on benchmark quantum circuits using noisy simulation environments derived from IBM Quantum hardware models demonstrate that the proposed framework reduces SWAP overhead and circuit depth while improving execution fidelity and the reliability of selecting high-quality mappings compared with conventional heuristic and evolutionary approaches. The results indicate that the integration of evolutionary optimization and quantum machine learning provides an effective solution for noise-aware qubit mapping in NISQ-era quantum compilation.
Algorithm-Aware (AlgAw) qubit mapping aims at directly providing the solutions to qubit mapping of algorithms with regular structures based on the algorithm’s features. Although the exact method provides a high-quality solution, its compilation time grows exponentially with the circuit size. To improve its scalability, we propose the AlgAw qubit mapping. The main idea is to first determine the subcircuits in an algorithm to be mapped, then analyze the optimal solutions of small-scale subcircuits found by exact methods to obtain solutions of large-scale subcircuits, and finally reconstruct the entire circuit and assign parameters. Applying AlgAw to the Quantum Approximate Optimization Algorithm (QAOA) on linear and T-shaped subtopologies produces optimal and scalable solutions for arbitrary numbers of qubits and depths, which is critical to the algorithm’s performance on Noisy Intermediate-Scale Quantum (NISQ) computers. Compared to Qiskit, Tket, and SWAP-Network, AlgAw produces the least number of CNOT gates and the lowest circuit depth. Furthermore, AlgAw takes only a few seconds to obtain a circuit with a hundred qubits that satisfies the connectivity constraints. The benchmarking results on Quantum Processing Units (QPUs) show that AlgAw qubit mapping yields higher values of approximation ratio than others. AlgAw can also be applied to other algorithms such as the Variational Quantum Eigensolver (VQE).
Abstract To execute quantum circuits on a quantum processor, they must be modified to meet the physical constraints of the quantum device. This process, called quantum circuit mapping , results in a gate/circuit depth overhead that depends on both the circuit properties and the hardware constraints, being the limited qubit connectivity a crucial restriction. In this paper, we propose to extend the characterization of quantum circuits by including qubit interaction graph properties using graph theory-based metrics in addition to previously used circuit-describing parameters. This approach allows for an in-depth analysis and clustering of quantum circuits and a comparison of performance when run on different quantum processors, aiding in developing better mapping techniques. Our study reveals a correlation between interaction graph-based parameters and mapping performance metrics for various existing configurations of quantum devices. We also provide a comprehensive collection of quantum circuits and algorithms for benchmarking future compilation techniques and quantum devices.
Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.
To run a quantum program in the real device, the compiler maps the logical qubits to physical qubits. This is the most crucial step of compiling a quantum circuit. Because the fidelity of a quantum circuit depends heavily on this mapping process. However, this qubit mapping problem is NP-complete. Therefore, we should resort to heuristics to find high-fidelity mappings. In this paper, we focused on finding efficient heuristic techniques to incorporate real-time error feedback and device connectivity information in order to achieve high fidelity mapping of the quantum circuits. We performed extensive analysis and experimental study based on two baseline algorithms. We performed our experimentation on various combinations of different error rates and heuristic techniques. Consequently, we designed very elegant techniques to consider both all types of real-time error feedback and connectivity information. We showed that our best heuristic approach performs \textbf{1.62x} ( on average) better than one baseline and \textbf{1.934x} ( on average ) better than the other baseline on random benchmarks. Finally, we compared our best heuristic ( CAES ) with the state-of-the-art heuristic-based mapping algorithm on representative benchmarks. We found that CAES performed \textbf{1.7x} ( on average ) better than the state of the art in terms of success rate.