To run a quantum program in the real device, the compiler maps the logical qubits to physical qubits. This is the most crucial step of compiling a quantum circuit. Because the fidelity of a quantum circuit depends heavily on this mapping process. However, this qubit mapping problem is NP-complete. Therefore, we should resort to heuristics to find high-fidelity mappings. In this paper, we focused on finding efficient heuristic techniques to incorporate real-time error feedback and device connectivity information in order to achieve high fidelity mapping of the quantum circuits. We performed extensive analysis and experimental study based on two baseline algorithms. We performed our experimentation on various combinations of different error rates and heuristic techniques. Consequently, we designed very elegant techniques to consider both all types of real-time error feedback and connectivity information. We showed that our best heuristic approach performs \textbf{1.62x} ( on average) better than one baseline and \textbf{1.934x} ( on average ) better than the other baseline on random benchmarks. Finally, we compared our best heuristic ( CAES ) with the state-of-the-art heuristic-based mapping algorithm on representative benchmarks. We found that CAES performed \textbf{1.7x} ( on average ) better than the state of the art in terms of success rate.
To run a quantum program in the real device, the compiler maps the logical qubits to physical qubits. This is the most crucial step of compiling a quantum circuit. Because the fidelity of a quantum circuit depends heavily on this mapping process. However, this qubit mapping problem is NP-complete. Therefore, we should resort to heuristics to find high-fidelity mappings. In this paper, we focused on finding efficient heuristic techniques to incorporate real-time error feedback and device connectivity information in order to achieve high fidelity mapping of the quantum circuits. We performed extensive analysis and experimental study based on two baseline algorithms. We performed our experimentation on various combinations of different error rates and heuristic techniques. Consequently, we designed very elegant techniques to consider both all types of real-time error feedback and connectivity information. We showed that our best heuristic approach performs \textbf{1.62x} ( on average) better than one baseline and \textbf{1.934x} ( on average ) better than the other baseline on random benchmarks. Finally, we compared our best heuristic ( CAES ) with the state-of-the-art heuristic-based mapping algorithm on representative benchmarks. We found that CAES performed \textbf{1.7x} ( on average ) better than the state of the art in terms of success rate.
We present a quantum circuit optimization technique that takes into account the variability in error rates that is inherent across present-day noisy quantum computing platforms.This method can be run after qubit routing or postcompilation and consists of computing isomorphic subgraphs to input circuits and scoring each using heuristic cost functions derived from system calibration data.Using an independent standard algorithmic test suite, we show that it is possible to recover on average nearly 40% of missing fidelity using better qubit selection via efficient to compute cost functions.We demonstrate additional performance gains by considering qubit placement over multiple quantum processors.The overhead from these tools is minimal with respect to other compilation steps, such as qubit routing, as the number of qubits increases.As such, our method can be used to find qubit mappings for problems at the scale of quantum advantage and beyond.
Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
Quantum circuit compilation is a critical step in realizing quantum algorithms on real quantum hardware. Traditional compilation methods often employ static optimization strategies, neglecting the unique constraints and characteristics of the target quantum device. This paper introduces a novel adaptive quantum circuit compilation framework designed to dynamically adjust circuit designs based on hardware-specific information, aiming to minimize gate count and, consequently, error rates. The core of the framework lies in integrating a hardware simulator directly within the compilation process. This allows the compiler to evaluate the performance of various circuit designs—considering factors like qubit connectivity, gate fidelity, and decoherence models—before committing to a final layout. The proposed approach represents a shift from static to adaptive optimization, providing a more nuanced and effective strategy for translating quantum algorithms into executable code on diverse quantum hardware platforms. This research demonstrates a significant potential improvement in quantum circuit efficiency and fidelity, addressing a key bottleneck in the advancement of quantum computing.
Running quantum programs on real hardware requires a compilation process in which qubit operations must be mapped onto physical resources, a task commonly referred to as the mapping problem. The objective is to choose a mapping that minimizes the execution time of the compiled program. This is critical because qubits are susceptible to decoherence, which limits the time available for computation. This thesis introduces an algorithm for addressing the mapping problem on the SpinBus architecture, a shuttling-based platform in which qubits can physically move and where certain types of conflicts must be considered. Because the mapping problem is believed to be computationally hard, our approach relies on heuristic strategies that do not guarantee optimality but produce high-quality solutions within practical time limits. We also develop a method for generating an initial qubit placement. We evaluate the proposed methods on a suite of benchmark circuits and compare them to a baseline mapping strategy. Our evaluation considers several metrics that capture the runtime of the mapping algorithm, the total amount of required shuttling, the likelihood of conflicts, and the achievable parallelism.
Compiling a high-level quantum circuit down to a low-level description that can be executed on state-of-the-art quantum computers is a crucial part of the software stack for quantum computing. One step in compiling a quantum circuit to some device is quantum circuit mapping, where the circuit is transformed such that it complies with the architecture’s limited qubit connectivity. Because the search space in quantum circuit mapping grows exponentially in the number of qubits, it is desirable to consider as few of the device’s physical qubits as possible in the process. Previous work conjectured that it suffices to consider only subarchitectures of a quantum computer composed of as many qubits as used in the circuit. In this work, we refute this conjecture and establish criteria for judging whether considering larger parts of the architecture might yield better solutions to the mapping problem. We show that determining subarchitectures that are of minimal size, i.e., from which no physical qubit can be removed without losing the optimal mapping solution for some quantum circuit, is a very hard problem. Based on a relaxation of the criteria for optimality, we introduce a relaxed consideration that still maintains optimality for practically relevant quantum circuits. Eventually, this results in two methods for computing near-optimal sets of subarchitectures—providing the basis for efficient quantum circuit mapping solutions. We demonstrate the benefits of this novel method for state-of-the-art quantum computers by IBM, Google, and Rigetti.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.