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Heuristic circuit mapping strategies for the SpinBus architecture

Martin Baum

Published Jan 1, 2025• 0 citations
Publisher

Abstract

Running quantum programs on real hardware requires a compilation process in which qubit operations must be mapped onto physical resources, a task commonly referred to as the mapping problem. The objective is to choose a mapping that minimizes the execution time of the compiled program. This is critical because qubits are susceptible to decoherence, which limits the time available for computation. This thesis introduces an algorithm for addressing the mapping problem on the SpinBus architecture, a shuttling-based platform in which qubits can physically move and where certain types of conflicts must be considered. Because the mapping problem is believed to be computationally hard, our approach relies on heuristic strategies that do not guarantee optimality but produce high-quality solutions within practical time limits. We also develop a method for generating an initial qubit placement. We evaluate the proposed methods on a suite of benchmark circuits and compare them to a baseline mapping strategy. Our evaluation considers several metrics that capture the runtime of the mapping algorithm, the total amount of required shuttling, the likelihood of conflicts, and the achievable parallelism.

DOI
10.18154/rwth-2026-02163

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Running quantum programs on real hardware requires a compilation process in which qubit operations must be mapped onto physical resources, a task commonly referred to as the mapping problem. The objective is to choose a mapping that minimizes the execution time of the compiled program. This is critical because qubits are susceptible to decoherence, which limits the time available for computation. This thesis introduces an algorithm for addressing the mapping problem on the SpinBus architecture, a shuttling-based platform in which qubits can physically move and where certain types of conflicts must be considered. Because the mapping problem is believed to be computationally hard, our approach relies on heuristic strategies that do not guarantee optimality but produce high-quality solutions within practical time limits. We also develop a method for generating an initial qubit placement. We evaluate the proposed methods on a suite of benchmark circuits and compare them to a baseline mapping strategy. Our evaluation considers several metrics that capture the runtime of the mapping algorithm, the total amount of required shuttling, the likelihood of conflicts, and the achievable parallelism.
In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.
Quantum circuits are typically represented by a (ordered) sequence of gates over a set of virtual qubits. During compilation, the virtual qubits of the gates are assigned to the physical qubits of the underlying quantum hardware, a step often referred to as the qubit assignment problem. To ensure that the resulting circuit respects hardware connectivity constraints, additional SWAP gates are inserted as needed, which is known as the qubit routing problem. Together, they are called the Qubit Mapping Problem (QMP), which is known to be NP-hard. A very common way to deal with the complexity of the QMP is to partition the sequence of gates into a sequence of gate groups (or layers). However, this imposes a couple of important restrictions: (1) SWAP gates can only be added between pairs of consecutive groups, and (2) all the gates belonging to a certain group have to be executed (in parallel) in the same time slot. The first one prevents gates to be re-arranged optimally, while the second one imposes a time discretization that practically ignores gate execution time. While this clearly reduces the size of the feasible space, little is still known about how much is actually lost by imposing a fixed layering when looking at the minimization of either the number of SWAPs or the makespan of the compiled circuit. In this paper, we present a flexible branch and bound algorithm for a generalized version of the QMP that either considers or ignores the gate layering and the gate execution time. The algorithm can find find proven optimal solutions for all variations of the QMP, but also offers a great platform for different heuristic algorithms. We present results on several benchmark sets of small quantum circuits, and we show how ignoring the layering can significantly improve some key performance indicators of the compiled circuit.
Quantum computing promises to solve certain problems more efficiently than classical computation. Realizing this potential on noisy, intermediate-scale quantum (NISQ) devices remains challenging. Among other things, hardware connectivity constraints necessitate additional routing operations that degrade circuit fidelity. The qubit mapping problem - assigning logical qubits to physical qubits while minimizing inserted SWAP gates - is thus critical in quantum circuit transpilation. Exact methods scale poorly, and heuristic approaches like the SABRE algorithm, though efficient, rely on local decisions that can miss globally optimal solutions. In this thesis, we propose K-SWAP SABRE that integrates bounded exhaustive search over sequences of up to k SWAPs into the SABRE algorithm. A modified heuristic ensures global progress while maintaining comparability between explored branches. Experiments on benchmark circuits show that increasing k reduces required SWAP gates, especially on highly connected devices, though at the cost of longer runtime. Our results demonstrate that K-SWAP SABRE can improve heuristic qubit mapping quality without sacrificing scalability, offering a practical approach for mapping circuits to near-term and emerging quantum architectures.
Executing quantum circuits on currently available quantum computers requires compiling them to a representation that conforms to all restrictions imposed by the targeted architecture. Due to the limited connectivity of the devices' physical qubits, an important step in the compilation process is to map the circuit in such a way that all its gates are executable on the hardware. Existing solutions delivering optimal solutions to this task are severely challenged by the exponential complexity of the problem. In this paper, we show that the search space of the mapping problem can be limited drastically while still preserving optimality. The proposed strategies are generic, architecture-independent, and can be adapted to various mapping methodologies. The findings are backed by both, theoretical considerations and experimental evaluations. Results confirm that, by limiting the search space, optimal solutions can be determined for instances that timeouted before or speed-ups of up to three orders of magnitude can be achieved.
Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.
Advanced neutral atom quantum systems are being developed by the industry due to its unique hardware features that enable efficient quantum circuit execution. In fact, neutral atom quantum systems are the only platforms that simultaneously support both long-range qubit interactions and native multi-qubit gates. However, the unique characteristics of neutral atom devices limit the applicability of existing qubit mapping methods developed for other quantum devices, and the state-of-the-art mapping approach [13] for neutral atom devices suffers from long runtime and low shuttle scheduling parallelism. We introduce a novel mapping and shuttling framework for neutral atom devices. We first partition the input circuit into a sequence of subcircuits, each associated with a mapping that enables the execution of all gates in the subcircuit. To find these mappings efficiently, we adopt a flexible strategy that dynamically switches between two mapping search methods. Then, for each pair of consecutive mappings, we schedule the shuttling operations required to transition between them and prioritize timing-critical operations to improve parallelism. We performed experiments on three benchmark sets, including circuits with up to 1617 qubits and more than 100,000\mathbf{1 0 0, 0 0 0}100,000 gates. Our proposed framework resulted in high-quality routing solutions and consistently achieves higher fidelity with shorter runtime compared to existing approaches.