Advanced neutral atom quantum systems are being developed by the industry due to its unique hardware features that enable efficient quantum circuit execution. In fact, neutral atom quantum systems are the only platforms that simultaneously support both long-range qubit interactions and native multi-qubit gates. However, the unique characteristics of neutral atom devices limit the applicability of existing qubit mapping methods developed for other quantum devices, and the state-of-the-art mapping approach [13] for neutral atom devices suffers from long runtime and low shuttle scheduling parallelism. We introduce a novel mapping and shuttling framework for neutral atom devices. We first partition the input circuit into a sequence of subcircuits, each associated with a mapping that enables the execution of all gates in the subcircuit. To find these mappings efficiently, we adopt a flexible strategy that dynamically switches between two mapping search methods. Then, for each pair of consecutive mappings, we schedule the shuttling operations required to transition between them and prioritize timing-critical operations to improve parallelism. We performed experiments on three benchmark sets, including circuits with up to 1617 qubits and more than $\mathbf{1 0 0, 0 0 0}$ gates. Our proposed framework resulted in high-quality routing solutions and consistently achieves higher fidelity with shorter runtime compared to existing approaches.
Advanced neutral atom quantum systems are being developed by the industry due to its unique hardware features that enable efficient quantum circuit execution. In fact, neutral atom quantum systems are the only platforms that simultaneously support both long-range qubit interactions and native multi-qubit gates. However, the unique characteristics of neutral atom devices limit the applicability of existing qubit mapping methods developed for other quantum devices, and the state-of-the-art mapping approach [13] for neutral atom devices suffers from long runtime and low shuttle scheduling parallelism. We introduce a novel mapping and shuttling framework for neutral atom devices. We first partition the input circuit into a sequence of subcircuits, each associated with a mapping that enables the execution of all gates in the subcircuit. To find these mappings efficiently, we adopt a flexible strategy that dynamically switches between two mapping search methods. Then, for each pair of consecutive mappings, we schedule the shuttling operations required to transition between them and prioritize timing-critical operations to improve parallelism. We performed experiments on three benchmark sets, including circuits with up to 1617 qubits and more than 100,000 gates. Our proposed framework resulted in high-quality routing solutions and consistently achieves higher fidelity with shorter runtime compared to existing approaches.
Quantum computing based on Neutral Atoms (NAs) provides a wide range of computational capabilities, encompassing high-fidelity long-range interactions with native multi-qubit gates and the ability to shuttle arrays of qubits. While, previously, these capabilities have been studied individually, we propose a fast hybrid compiler to perform circuit mapping and routing utilizing both high-fidelity gate interactions and qubit shuttling. We delve into the intricacies of the compilation process when combining multiple capabilities and present effective solutions to address the resulting challenges. The final compilation strategy is then showcased across various hardware settings, revealing its versatility, and highlighting potential fidelity enhancements achieved through the strategic utilization of combined gate- and shuttling-based routing. With the additional multi-qubit gate support for both routing capabilities, the proposed approach is able to take advantage of the full spectrum of computational capabilities offered by NAs.
Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform because of their long qubit coherence, flexible qubit arrangement, and multiqubit gate capabilities. However, circuit execution often requires physically moving qubits, making compilation a critical optimization challenge. We propose a circuit independent mathematical framework built on graph-theoretic combinatorial optimization that determines the minimal number of required qubit transfers. This model captures spatial constraints specific to NAQC platforms with zone-limited gate operations and multi-qubit gates. From this framework, we encode the qubit mapping problem as a nonlinear integer program and solve it using a genetic algorithm, enabling trade-offs between minimizing the total traveled distance and the number of parallel transfer operations. Compared to the state-of-the-art scalable compiler for zoned architectures, our approach consistently finds fewer transfers. Depending on the optimization focus, our method produces shorter traveled distances or fewer parallel transfer operations. This work provides both theoretical guaranties and a practical tool for efficient, architecture-aware quantum circuit compilation. As a result, practitioners can generate hardware-aware mappings that reduce movement-induced errors and better exploit atom transfer parallelism, directly improving execution efficiency on NAQC devices.
Neutral atom quantum computers (NAQCs) are emerging as a highly promising platform for scalable quantum computing, thanks to their long qubit coherence times, flexible qubit layouts, and ability to implement multi-qubit gates [1]. Despite these advantages,executing circuits often requires moving qubits physically, which makes compilation a crucial and challenging optimization task. To address this, we developed a circuit-independent compiler framework based on graph theory that determines the minimum number of qubit transfers needed, including those involved in multi-qubit gates. This model captures the spatial restrictions inherent to NAQC platforms with zone-limited gate operations. Using this framework, we formulated the qubit mapping problem as a nonlinear integer program and solved it with a genetic algorithm, enabling control over trade-offs between the total distance qubits travel and the number of parallel transfer operations (PTOs). When benchmarked against the leading ZAC compiler [2], our approach consistently reduces the number of qubit transfers. Depending on the optimization goal, it can either shorten the overall travel distance or minimize PTOs. The work presented in this poster thus provides a tool for efficient, architecture-aware quantum circuit compilation. [1] Ludwig Schmid et al, “Computational capabilities and compiler development for neutral atom quantum processors—connecting tool developers and hardware experts”, Quantum Sci. Technol. 9 033001, doi: 10.1088/2058-9565/ad33ac (2024) [2] W. Lin, D. B. Tan and J. Cong, “Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms”, IEEE International Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, USA, 2025, pp. 127-142, doi: 10.1109/HPCA61900.2025.00021 (2025
Neutral atoms are a promising choice for scalable quantum computing architectures. Features such as long distance interactions and native multiqubit gates offer reductions in communication costs and operation count. However, the trapped atoms used as qubits can be lost over the course of computation and due to adverse environmental factors. The value of a lost computation qubit cannot be recovered and requires the reloading of the array and rerunning of the computation, greatly increasing the number of runs of a circuit. Software mitigation strategies exist [1] but exhaust the original mapped locations of the circuit slowly and create more spread out clusters of qubits across the architecture decreasing the probability of success. We increase flexibility by developing strategies that find all reachable qubits, rather only adjacent hardware qubits. Second, we divide the architecture into separate sections, and run the circuit in each section, free of lost atoms. Provided the architecture is large enough, this resets the circuit without having to reload the entire architecture. This increases the number of effective shots before reloading by a factor of two for a circuit that utilizes 30% of the architecture. We also explore using these sections to parallelize execution of circuits, reducing the overall runtime by a total 50% for 30 qubit circuit. These techniques contribute to a dynamic new set of strategies to combat the detrimental effects of lost computational space.
Advanced silicon-based spin-qubit chips are being developed by the industry because of its promising scalability for large-scale quantum computing. The silicon-based fabrication of spin-qubit devices allows them to scale to thousands of qubits while maintaining a relatively small area compared to other quantum technologies such as superconducting or neutral atom. However, the unique characteristics of spin-qubit devices limit the applicability of existing qubit routing methods developed for other quantum devices, and the state-of-the-art routing approach for spin-qubit devices overlooks some key factors, leading to suboptimal solution quality. We introduce a novel routing method for spin-qubit devices that leverages Dijkstra’s algorithm and breadth-first search to determine the routing path for the operand qubit(s) of each gate. To avoid redundant computations for routing paths, we determine the routing region for each gate and represent it as a bit vector, which enables efficient overlap checking between routing regions. We performed experiments on four benchmark sets, including circuits with up to 1617 qubits and more than 700,000 gates. These benchmark sets cover a wide range of quantum circuits, including reversible arithmetic, algorithmic, synthesized, and random circuits. Our proposed method resulted in high-quality routing solutions and outperformed the state-of-the-art qubit routing approach on spin-qubit devices with over 29% and 7% reduction in operation overhead and depth overhead, respectively.
Quantum computing is transitioning from an academic idea to a practical technology, driven by recent hardware advancements and clear paths toward real-world applications. Universal quantum ecosystems (e.g., Qiskit, Cirq, PennyLane) facilitate this transition by providing a consistent interface to diverse quantum devices, abstracting hardware-specific details through a device model that captures each device's computational capabilities. However, these device models have historically been shaped by superconducting hardware, assuming static qubit positions and fixed coupling maps. This prevents them from representing the unique computational capabilities of emerging technologies such as neutral atoms, which feature dynamic qubit rearrangement and zoned operations. As a result, although numerous specialized compilers for neutral atom devices already exist, they cannot retrieve the hardware information they need through these ecosystems - creating a technology lock that hinders or even prevents the integration of neutral atom devices. In this work, we demonstrate how this limitation leads to suboptimal compilation results and can exclude certain devices entirely. Motivated by this, we propose rethinking current device models to faithfully represent neutral atom devices, enabling their seamless integration into universal quantum ecosystems. Evaluations conducted within the Quantum Device Management Interface (QDMI) demonstrate that the proposed device model unlocks a routing overhead fidelity improvement by a factor of up to 100,000 on a circuit with 16 qubits and 600 gates.