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IEEE Transactions on Applied Superconductivity

Binary Counters Using Adiabatic Quantum-Flux-Parametron Logic

Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa

Published Dec 14, 2020• 12 citations
Publisher

Abstract

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this article, we design binary counters, namely an up counter, a down counter, and an up/down counter, based on AQFP logic. These binary counters are T-flip-flop-based and count logic 1s in the input signal that is synchronized with excitation currents, which clock the counters. The internal state of a T flip-flop changes when the internal state of the previous T flip-flop changes from logic 1 to 0 and from logic 0 to 1 for the count-up and count-down operations, respectively. Each internal state of a T flip-flop is read out serially by a buffer chain coupled to the T flip-flops. We fabricate 4-bit up, down, and up/down counters using the AIST 10 kA/cm2Nb high-speed standard process and demonstrate their correct operation at low frequency. This is the first demonstration of binary counters based on AQFP logic.

DOI
10.1109/tasc.2020.3044677

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Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this article, we design binary counters, namely an up counter, a down counter, and an up/down counter, based on AQFP logic. These binary counters are T-flip-flop-based and count logic 1s in the input signal that is synchronized with excitation currents, which clock the counters. The internal state of a T flip-flop changes when the internal state of the previous T flip-flop changes from logic 1 to 0 and from logic 0 to 1 for the count-up and count-down operations, respectively. Each internal state of a T flip-flop is read out serially by a buffer chain coupled to the T flip-flops. We fabricate 4-bit up, down, and up/down counters using the AIST 10 kA/cm2Nb high-speed standard process and demonstrate their correct operation at low frequency. This is the first demonstration of binary counters based on AQFP logic.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.
We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.
We report recent progress on adiabatic quantum-flux-parametron (AQFP) logic, which is an energy-efficient superconductor logic based on quantum flux parametron (QFP). The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching, in which the shape of the potential energy gradually varies between single-well and double-well shapes as the result of using ac excitation magnetic fluxes. First, we show the operation principle of AQFP and explain adiabatic switching in light of potential energy shapes. We also show calculated switching energy and bit error rates to demonstrate that the switching energy of AQFP can be significantly reduced while keeping a low error rate. Then, we report recently developed AQFP subsystems, which include an 8-bit carry look-ahead adder, a register file, and a long-interconnect driver. Our demonstration reveals that AQFP technology is ready to be applied in microprocessor design.