Oxide-First-Metal-Last (OFML) approach was developed and implemented for surface electrode ion trap after different fabrication approaches evaluation. Surface electrode ion trap was fabricated on the high resistivity wafer after lithographic process optimization and metal electrode corrosion troubleshooting. Less than 10E-12A leakage current between surface electrodes was achieved when swept voltage from -100V to 100V.
Oxide-First-Metal-Last (OFML) approach was developed and implemented for surface electrode ion trap after different fabrication approaches evaluation. Surface electrode ion trap was fabricated on the high resistivity wafer after lithographic process optimization and metal electrode corrosion troubleshooting. Less than 10E-12A leakage current between surface electrodes was achieved when swept voltage from -100V to 100V.
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of40μmare evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB andQfactor increment of 2 and 6 for the corresponding trap types.
Surface electrode ion trap on different substrates (i.e., high-resistivity (HR) silicon, silicon with grounding plane, and glass) are designed and fabricated. Performance comparison of these substrates is carried out in terms of leakage current, parasitic capacitance and RF loss. It is found that ion trap fabricated on glass has superior RF performance, but the leakage current between center electrodes can be as high as 10-8A, limiting the maximum RF voltage allowed in the ion trap. For traps on silicon with grounding plane, on-chip insertion loss (S21) is reduced by ~4.6 dB and resonance peak power after packaging is improved by ~10 dBm, compared with traps on HR silicon. Ion trapping operation is carried out on glass traps, where a single ion can be trapped for several hours with Doppler cooling.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Trapped ions in Paul traps (radio frequency ion traps) are a promising candidate for the realization of a quantum computer. To date, experimental demonstrations of quantum computing and information processing with trapped ions have been limited to small numbers of quantum bits (qubits). The most prominent challenge to realise ion-trap quantum computation is to scale the system and control a large number of trapped ions coherently. Surface-electrode ion trap designs which are amenable to various microfabrication techniques offer a path to achieve this. In this work, design, fabrication and key operations of two types of surface-electrode ion traps, i.e. a Y-junction trap and a two-dimensional (2D) hexagonal lattice trap developed towards scaling ion-trap architectures, are presented. The steps involved in the fabrication of the ion-trap devices included photolithography, wet etch (hydrofluoric acid etch) and dry etch (deep reactive ion and inductively coupled plasma etching), and metal evaporation. The devices were fabricated on SOI substrates with different buried oxide thicknesses (i.e. 5 µm and 10 µm) and different metals for the trap electrodes (i.e. gold and aluminium). An extremely high-breakdown voltage up to 1 kV was measured in vacuum for the SOI-built test devices with a 10 µm-thick buried oxide formed by oxide film-to-oxide film bonding process. This is attributed to the deep V-shaped undercut profile of the buried oxide layer which resulted in a large breakdown path length, and so mitigating surface breakdown effects. Owing to the V-shaped undercut profile, the surface breakdown voltage was improved by 15% for the devices fabricated on SOI substrates with a 10 µm-thick buried oxide. In the first experiment, the demonstration of ytterbium (174Yb+) ion trapping in the 2D hexagonal lattice trap is achieved with a relatively long lifetime of a laser-cooled ion up to 90 minutes and ≤ 5 minutes without cooling in ultra-high vacuum system. The 2D lattice trap design allows for reliable trapping of 2D ion lattices, rudimentary shuttling between lattice sites and deterministic introducing of defects into the ion lattice. Based on all these abilities, such a 2D lattice trap with the predicted reduction of lattice spacing down to 32 µm can be configured as a versatile architecture for 2D quantum simulations with trapped ions. In the second experiment, microparticle trapping in the 2D lattice trap, performed in air, is achieved with the longest trapping lifetime of 60 minutes. Both gold and aluminium-coated electrodes also lead to comparable trapping performances. Furthermore, the in situ levitation of microparticles is successfully demonstrated at the maximum levitation height of 30 µm. This ability provides additional control on the trapping height which increases the overall functionality of the 2D lattice trap.
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.
In this work, we report ion trap fabrication using prevailing foundry copper back-end-of-line process on a 300mm Si platform. Surface electrodes comprising of ~3.7 µm thick Cu and ~0.2 µm thick of Au surface finish are electroplated above a ~3 µm thick of SiO2 layer on a high-resistivity Si substrate. The innovative process, which is fully compatible with CMOS back-end, enables a fine gap trench structure between the electrodes, such that the exposed dielectric area to the trapped ions is reduced. By optimizing the electroplating process, a relatively flat Cu surface is created with a thin Au layer deposited as an effective protective layer to prevent surface oxidation. The fabricated trap is wire-bonded in a CPGA package for DC and RF testing. Small size Si traps show a good RF dissipation property which is a prerequisite for ion trapping. The further integration of TSV and Si photonics shows a promising prospect in terms of electrical and optical performance enhancement of ion trap.