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Bulletin of the American Physical Society

Demonstration of the QCCD trapped-ion quantum computer architecture

Steven A. Moses, Juan Miguel Rey Pino, Joan Dreiling, Caroline Figgatt, John Gaebler, Michael S. Allman, Charles H. Baldwin, Michael Foss‐Feig, David Hayes, Karl Mayer, Ciarán Ryan-Anderson, Brian Neyenhuis

Published Jun 4, 2020• 1 citation
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The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=642^6=6426=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.