Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).

Scientific ReportsMay 20, 20260 citations

A Feasible Design of Elementary Quantum Arithmetic Logic Units for Near-Term Quantum Computers

Junxu Li

Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and $C\sqrt{X}$ (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and $C\sqrt{X}$ (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.

arXiv:2408.06561Aug 13, 20240 citations

Fault-Tolerant Quantum Realization of Nikhilam Multiplier with Clifford+T-group

Laxmidhar Biswal, Anirban Bhattacharjee, Chandan Bandyopadhyay +1 more

SN Computer ScienceJan 23, 20261 citation

A New Quantum Efficient Fault Tolerant Parity Preserving Clifford + T ALU

Shekoofeh Moghimi, Mohammad Reza Reshadinezhad, Antonio Rubio

Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.

IEEE Transactions on Emerging Topics in ComputingApr 1, 20260 citations

No-Go Theorem on Fault Tolerant Gadgets for Multiple Logical Qubits

Aranya Chakraborty, Daniel Gottesman

Identifying stabilizer codes that admit fault-tolerant implementations of the full logical Clifford group would significantly advance fault-tolerant quantum computation. Motivated by this goal, we study several classes of fault-tolerant gadget constructions consisting of Clifford gates acting on the physical qubits, including transversal gadgets, code automorphisms, and fold-transversal gadgets. While stabilizer codes encoding a single logical qubit, most notably the [[7,1,3]] Steane code, are known to admit transversal implementations of the full logical Clifford group, no analogous examples are known for codes encoding multiple logical qubits. In this work, we prove a no-go theorem establishing that no stabilizer code admits a fully transversal implementation of the Clifford group on more than one logical qubit. We further strengthen this result by showing that fold-transversal implementations of the full logical Clifford group are impossible for stabilizer codes encoding more than two logical qubits. More generally, we introduce the notion of k-fold transversal gadgets and prove that implementing the full Clifford group on k logical qubits requires at least k-fold transversal gadgets at the physical level. In addition, we analyze code-automorphism based constructions and demonstrate that they also fail to realize the full Clifford group on multiple logical qubits for any stabilizer code. Together, these results place fundamental constraints on fault-tolerant Clifford gadget design and show that stabilizer codes supporting the full logical Clifford group on multiple logical qubits via these architectures do not exist. Since the Clifford group is a core component of universal gate sets, our findings imply that quantum computing with codes encoding multiple logical qubits within a single code block necessarily entails more complex constructions for fault tolerance.Identifying stabilizer codes that admit fault-tolerant implementations of the full logical Clifford group would significantly advance fault-tolerant quantum computation. Motivated by this goal, we study several classes of fault-tolerant gadget constructions consisting of Clifford gates acting on the physical qubits, including transversal gadgets, code automorphisms, and fold-transversal gadgets. While stabilizer codes encoding a single logical qubit, most notably the [[7,1,3]] Steane code, are known to admit transversal implementations of the full logical Clifford group, no analogous examples are known for codes encoding multiple logical qubits. In this work, we prove a no-go theorem establishing that no stabilizer code admits a fully transversal implementation of the Clifford group on more than one logical qubit. We further strengthen this result by showing that fold-transversal implementations of the full logical Clifford group are impossible for stabilizer codes encoding more than two logical qubits. More generally, we introduce the notion of k-fold transversal gadgets and prove that implementing the full Clifford group on k logical qubits requires at least k-fold transversal gadgets at the physical level. In addition, we analyze code-automorphism based constructions and demonstrate that they also fail to realize the full Clifford group on multiple logical qubits for any stabilizer code. Together, these results place fundamental constraints on fault-tolerant Clifford gadget design and show that stabilizer codes supporting the full logical Clifford group on multiple logical qubits via these architectures do not exist. Since the Clifford group is a core component of universal gate sets, our findings imply that quantum computing with codes encoding multiple logical qubits within a single code block necessarily entails more complex constructions for fault tolerance.

quant-pharXiv:2602.13395PRX QuantumFeb 17, 20260 citations

C\sqrt{X}

(CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.