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Scientific Reports

Design of a fault‑tolerant‑metric‑aware, reversible n‑bit quantum arithmetic logic unit using IBM Qiskit

Agniswar Banerjee

Published May 20, 2026• 0 citations
Publisher

Abstract

Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).

DOI
10.1038/s41598-026-53845-1

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Abstract This paper presents a reversible, n‑bit Quantum Arithmetic Logic Unit (QALU) implemented in Qiskit that supports a classical ALU‑like instruction set: ADD, SUB, CMP, AND/OR/XOR and their negations, unary NOT, shifts and rotates, and operand passthrough. The QALU outputs a result register and status flags N, Z, C, V (negative, zero, carry/no‑borrow, signed overflow) and emits explicit comparison outputs EQ, LT u , LT s . The design is modular and operation‑selectable at compile time, enabling clean verification and resource accounting. To evaluate fault‑tolerant efficiency, the circuits are decomposed into a Clifford + T basis and measure T‑count alongside CX‑count and depth. Exhaustive verification on Aer (matrix‑product‑state simulation) confirms correctness for all input pairs for n = 4 across 16 operations. Hardware experiments on IBM Quantum (limited to n = 2) demonstrate end‑to‑end execution with dynamical decoupling and gate twirling, and readout mitigation via mthree. An analytical scaling discussion grounded in ripple‑carry adder theory and known Toffoli/T‑gate constructions is further provided. These results show that a practical, verifiable QALU with flags and compare can be implemented within Qiskit while exposing meaningful fault‑tolerant metrics and hardware‑realistic performance characterization. Key findings from the provided implementation artifacts: (1) Aer exhaustive verification (n = 4): the QALU was exhaustively tested over all 2 2n =256 input pairs for each of 16 operations (4096 total tests), with 0 mismatches against a classical reference model. (2) Resource metrics (n = 4): after transpilation to a Clifford + T‑style basis {cx, h, s, sdg, x, z, t, tdg} at optimization level 3, the highest‑cost operations (ADD, SUB, CMP) report T‑count = 86, CX‑count ≈ 102–106, and depth ≈ 138 on a 24‑qubit circuit instance (including flags and MCX ancillae). (3) IBM hardware test (n = 2): on an automatically selected IBM backend (ibm_torino) using dynamical decoupling and gate twirling plus mthree readout mitigation, an exhaustive run over all 256 circuits yielded raw correctness 91.41% and mitigated correctness 91.02% (slightly worse post‑mitigation, consistent with practical tradeoffs where mitigation noise/calibration drift can dominate at small sizes).
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.
Quantum Arithmetic Logic Units (ALUs) serve as critical components in quantum processors, enabling both arithmetic and logical operations on qubits. However, the fragile nature of quantum systems makes them susceptible to errors and decoherence, necessitating fault-tolerant designs. In this work, we propose a fault-tolerant quantum ALU architecture constructed using the Clifford+ T gate set, which is widely recognized for its compatibility with error-correcting codes. The proposed design minimizes quantum resource overhead while maintaining computational accuracy under fault-prone conditions. Notably, the architecture requires zero ancilla and generates a single garbage output, optimizing the qubit space. Performance evaluations demonstrate significant improvements, achieving a 31.8% reduction in T-count and a 33.3% reduction in T-depth compared to existing designs. These enhancements contribute to more efficient and reliable quantum computation, paving the way for scalable quantum processor development.
Arithmetic units constitute fundamental components of reversible-computing architectures, where circuit complexity, resource utilization, and hardware realizability are critical design considerations. This work presents a parity-preserving reversible 2 × 2 Vedic multiplier architecture constructed using existing N1, RF, A, and N3 reversible logic blocks and hierarchically extended to realize a 4 × 4 multiplier through a parity-preserving 4-bit ripple-carry adder structure. Comparative evaluation demonstrates competitive performance relative to representative reversible multiplier architectures. To evaluate implementation-oriented characteristics, the proposed architecture was mapped to the Clifford+T gate set and analyzed using hardware-aware resource metrics. The resulting realization exhibits a T-count of 35, a T-depth of 19, and a transpiled circuit depth of 55 without requiring SWAP operations. The proposed 2 × 2 multiplier core was experimentally validated on the IBM Quantum ibm_kingston superconducting processor based on the Heron r2 architecture through complete truth-table verification across all sixteen input combinations using 1024 measurement shots per experiment. The dominant measured output matched the expected multiplication result in every case, yielding an average success probability of 70.12% and an average Bhattacharyya fidelity of 0.7012. Calibration-based fidelity estimation using backend-reported gate fidelities yielded an estimated circuit fidelity of 0.7485, which is consistent with the experimentally observed average success probability of 70.12%. Hardware-aware circuit characterization, noise-model evaluation, and fidelity analysis were performed to assess implementation behavior under practical execution conditions. In addition, application-level arithmetic demonstrations involving Low-bit-width image-processing arithmetic examples were used solely as application-level demonstrations of multiplier functionality and do not constitute a complete quantum image-processing framework. The obtained results confirm the functional correctness, hardware compatibility, and resource efficiency of the proposed architecture and provide practical insights for future reversible arithmetic and quantum-computing applications.
Efficient quantum arithmetic is a prerequisite for the practical realization of large-scale quantum algorithms, yet many resource-optimized designs remain at the theoretical level. In this work, we present a complete implementation of the T-count-optimized non-restoring quantum square-root circuit proposed by Muñoz-Coreas E. and Thapliyal H. in the Qrisp quantum programming framework. The implemented design follows the garbageless square-root construction based on reversible arithmetic and is built from modular sub-circuits, including reversible adders, subtractors, controlled add/subtract blocks, and controlled adders. We show that the high-level abstractions provided by Qrisp enable a direct and reusable realization of the algorithm while preserving the theoretical resource advantages of the original circuit. To assess practical feasibility, the circuits were additionally executed on IBM’s ibm_marrakesh superconducting quantum processor. The experimental results show that the algorithm can run on contemporary NISQ hardware for small input sizes, although compilation overhead, two-qubit gate errors, readout errors, and relaxation effects significantly reduce success rates as the circuit size increases. Among the tested runtime techniques, dynamical decoupling provided only limited improvement. These results establish the practical realizability of a resource-efficient quantum square-root circuit and provide insight into the challenges of executing arithmetic-heavy quantum algorithms on present-day hardware. These results demonstrate that the previously proposed T-count-optimized non-restoring square-root circuit can be realized as a modular Qrisp implementation, exported to Qiskit, and experimentally evaluated on contemporary NISQ hardware, while also highlighting the practical limitations imposed by compilation overhead and hardware noise.
Reversible logic is essential in quantum computing due to its ability to preserve information and establish a one-to-one mapping between inputs and outputs. The Clifford+T gate set, known for supporting fault-tolerant quantum circuits, offers resilience against decoherence but introduces high implementation costs, particularly due to the T gate's resource intensity. In this work, we propose a new and efficient quantum multiplexer design, the Quantum Clifford T-MUX, designed entirely within the Clifford+T framework. This multiplexer minimizes T-count and avoids the use of ancillary qubits, both critical factors for practical, fault-tolerant quantum computing. As part of this architecture, we present a newly designed fault-tolerant Peres gate using only Clifford+T gates, which serves as a fundamental building block in the T-MUX construction. The proposed T-MUX achieves reduced T-count, no garbage output, and improved efficiency compared to traditional designs. These improvements position it as a valuable component for building scalable quantum Arithmetic Logic Units (ALUs), data buses, and memory systems. Overall, this work contributes toward the development of low-overhead, modular quantum control structures suited for near-term and long-term quantum computing architectures. The proposed circuit is simulated using the Quirk online tool, and the result confirms the accuracy of the design. This design achieves an average 35% improvement in T-Count without any constant input, compared to its counterpart, respectively.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.