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T-count and T-depth efficient fault-tolerant quantum arithmetic and logic unit

Sarallah Keshavarz, Mohammad Reza Reshadinezhad, Shekoofeh Moghimi

Published Jun 24, 2024• 7 citations
Publisher
DOI
10.1007/s11128-024-04456-0

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Quantum Arithmetic Logic Units (ALUs) serve as critical components in quantum processors, enabling both arithmetic and logical operations on qubits. However, the fragile nature of quantum systems makes them susceptible to errors and decoherence, necessitating fault-tolerant designs. In this work, we propose a fault-tolerant quantum ALU architecture constructed using the Clifford+ T gate set, which is widely recognized for its compatibility with error-correcting codes. The proposed design minimizes quantum resource overhead while maintaining computational accuracy under fault-prone conditions. Notably, the architecture requires zero ancilla and generates a single garbage output, optimizing the qubit space. Performance evaluations demonstrate significant improvements, achieving a 31.8% reduction in T-count and a 33.3% reduction in T-depth compared to existing designs. These enhancements contribute to more efficient and reliable quantum computation, paving the way for scalable quantum processor development.
Reversible logic is characterized by its feature of being a prominent application in low-power conventional computers and the most compatible logic in quantum computers. Quantum circuits executes quantum algorithms and are important in a new generation of advanced computing. However, they are highly error-prone and also subject to the use of limited and sensitive physical resources like qubits and quantum gates. This paper introduces a comprehensive fault tolerant quantum-based reversible circuit which can calculate a high variety number of arithmetic and logic operations. It uses both: parity preserving method for detecting one or an odd number of bit errors, and Clifford + T implementation for protecting circuits against decoherence faults. First, we propose a new fault-tolerant (parity preserving and Clifford + T) adder/subtractor and derive a quantum reversible Arithmetic and Logic Unit (ALU). These modules reach the most optimized extent of circuit line, ancilla inputs, and garbage outputs according to the logical analysis done in this work. This article focuses on reducing T-cost metrics in conjunction with enhancing the number of operations and quantum costs in proposed circuits compared to other counterparts. We propose 4-bit fault tolerant ALU derived from our proposed single-bit module to show the proposed circuit can be extended to any larger size. The proposed circuit is implemented in the Qiskit simulation tool, and output results confirm the accuracy of our design functionality. The proposed full adder/ subtractor achieves an average of 64% and 43%, and the proposed ALU circuit achieves an average of 38% and 27% improvement in T-count and T-depth, respectively compared to their counterparts. The proposed reversible quantum-optimized fault tolerant adder/subtractor and ALU units can be applied as the basic part of DSP systems and quantum processor units in quantum computing devices.
The Toffoli gate is a fundamental building block for quantum arithmetic and reversible logic, yet its efficient realization remains a major challenge in both near-term and fault-tolerant quantum architectures. Recent advances in dynamic quantum circuit capabilities, including mid-circuit measurement and classical feedforward, provide new opportunities for reducing the resource overhead of non-Clifford operations. In this work, we propose a set of dynamic decomposition strategies for multi-controlled Toffoli gates that exploit adaptive circuit execution and ancilla-assisted constructions. Our methods systematically reduce entangling-gate count, T-count, and T-depth compared with conventional static decompositions, while preserving fault-tolerance guarantees. Through analytical cost models and experimental evaluation, we demonstrate that relative-phase primitives and measurement-conditioned corrections enable scalable implementations with improved depth and resource efficiency.