In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc. In this paper, the authors show the design of a cost effective reversible programmable logic array using VHDL. It is simulated on Xilinx ISE 8.2i and results are shown. The proposed reversible Programming logic array called RPLA is designed by MUX gate & Feynman gate for 3- inputs, which is able to perform any reversible 3- input logic function or Boolean function. Furthermore the quantized analysis with comparative finding is shown for the realized RPLA against the existing one. The result shows improvement in the quantum cost and total logical calculation in proposed RPLA.
In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc. In this paper, the authors show the design of a cost effective reversible programmable logic array using VHDL. It is simulated on Xilinx ISE 8.2i and results are shown. The proposed reversible Programming logic array called RPLA is designed by MUX gate & Feynman gate for 3- inputs, which is able to perform any reversible 3- input logic function or Boolean function. Furthermore the quantized analysis with comparative finding is shown for the realized RPLA against the existing one. The result shows improvement in the quantum cost and total logical calculation in proposed RPLA.
In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc.In this paper, the authors show the design of a cost effective reversible programmable logic array using VHDL.It is simulated on Xilinx ISE 8.2i and results are shown.The proposed reversible Programming logic array called RPLA is designed by MUX gate & Feynman gate for 3-inputs, which is able to perform any reversible 3-input logic function or Boolean function.Furthermore the quantized analysis with comparative finding is shown for the realized RPLA against the existing one.The result shows improvement in the quantum cost and total logical calculation in proposed RPLA.
In EDA, Reversible logic has its applications in designing computer graphics, digital signal processing, quantum computing, nanotechnology and cryptography. It is a prospective design style in quantum computing and modern nanotechnology. Although noteworthy proposals have been put forth towards defining new reversible logic gates and sub units of ALUs, design of efficient Multiplier block remains crucial to the realization of a high-performance Reversible Logic ALU that can be leveraged by Deep Neural Networks for high performance MAC operations. This paper proposes the design and comparison of a component scalable Reversible Logic Multiplier using the proposed SAK gate. The verification and simulation have been carried out using Vivado® by Xilinx and further implemented on an Artix®-7 based cost effective FPGA. The proposed design has 27% lesser Gate Count and 12.5% lesser Quantum Cost compared to prior designs.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.
Reversible logic provides a foundation for nextgeneration computing systems, particularly in quantum and emerging nanotechnology-based architectures. Unlike conventional logic, reversible gates preserve information and support backward computation, making them crucial for designing quantum circuits. This paper introduces a reversible Arithmetic and Logic Unit (ALU) that performs eight fundamental operations-AND, OR, NOT, XOR, addition, subtraction, increment, and decrement-using Fredkin, Peres, TR, and modified Fredkin gates. A dedicated control unit manages operation selection, ensuring functional flexibility and circuit efficiency. The proposed design achieves significant improvements by minimizing ancilla inputs, quantum cost and garbage outputs, resulting in a total quantum cost of 71 and contains 16 reversible gates and 14 garbage outputs. The architecture was modeled and verified using Xilinx Vivado HLS and ISE 14.7, and implemented on the Nexys A7 (Artix-7) FPGA platform. Comparative analysis demonstrates better efficiency than existing reversible ALU designs, establishing the proposed circuit as a strong candidate for quantum computing and other advanced computing paradigms.