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Circuits Systems and Signal Processing

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

K. Saranya, K. N. Vijeyakumar

Published Sep 25, 2020• 5 citations
Publisher
DOI
10.1007/s00034-020-01549-w

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quant-pharXiv:2512.01883•Dec 2, 2025•0 citations
At present, the reduction of circuit design power is a prime research topic. The reversible computation satisfies the criteria of the power consumption reduction compared to the traditional logic design. Thereby, reversible computation is gaining much attention in recent decades. Two reversible design approaches of binary-coded-decimal (BCD) to densely-packed-decimal (DPD) converter (encoder) and two design approaches of DPD to BCD converter (decoder) are proposed in this paper. The designs are carried out through the appropriate selection of the gates and further proper organization of such gates with parallel implementation. The proposed design approaches offer a low quantum cost implementation compared to state-of-the-art design. The cost results analysis of reversible DPD encoder shows appreciable reduction by at least ~23%, and that of decoder by at least ~62% compared to the state-of-art design found in the literature. Furthermore, the structures are decomposed into the primitive-quantum-gates and compressed in compact form for delay calculation
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.