The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.

quant-pharXiv:2512.01883Dec 2, 20250 citations

Design and Development of Cost Optimized Quantum Binary-Coded Decimal Adder using Reversible Logic Gates

Parna Kundu, Mousom Chatterjee, Susmita Biswas +6 more

Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.

ES GeneralJan 1, 20250 citations