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Symposium on VLSI Circuits

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor using 1.4zJ/op Superconductor Josephson Junction Devices

Christopher Lawrence Ayala, Tomoyuki Tanaka, Ro Saito, Mai Nozoe, Naoki Takeuchi, Nobuyuki Yoshikawa

Published Jun 1, 2020• 10 citations
Publisher

Abstract

We present an adiabatic microprocessor based on Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4b data words. We demonstrate register file R/W access, ALU execution, and program branching performed at 100kHz under the cryogenic temperature of 4.2K. We also successfully demonstrated a high-speed chip of the microprocessor execution units up to 2.5GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP) which has a switching energy of 1.4zJ when driven by a 4-phase 5GHz ac-clock at 4.2K.

DOI
10.1109/vlsicircuits18222.2020.9162792

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We present an adiabatic microprocessor based on Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4b data words. We demonstrate register file R/W access, ALU execution, and program branching performed at 100kHz under the cryogenic temperature of 4.2K. We also successfully demonstrated a high-speed chip of the microprocessor execution units up to 2.5GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP) which has a switching energy of 1.4zJ when driven by a 4-phase 5GHz ac-clock at 4.2K.
We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
We report recent progress on adiabatic quantum-flux-parametron (AQFP) logic, which is an energy-efficient superconductor logic based on quantum flux parametron (QFP). The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching, in which the shape of the potential energy gradually varies between single-well and double-well shapes as the result of using ac excitation magnetic fluxes. First, we show the operation principle of AQFP and explain adiabatic switching in light of potential energy shapes. We also show calculated switching energy and bit error rates to demonstrate that the switching energy of AQFP can be significantly reduced while keeping a low error rate. Then, we report recently developed AQFP subsystems, which include an 8-bit carry look-ahead adder, a register file, and a long-interconnect driver. Our demonstration reveals that AQFP technology is ready to be applied in microprocessor design.
Superconductor/ferromagnet/superconductor Josephson junctions across which the phases of superconducting order parameters are shifted by π in the ground state are called π Josephson junctions (π-JJs). Recently, several groups have established the fabrication technology of π-JJs so that superconductor logic families exploit π-JJs to improve circuit performance. In this paper, we investigate the advantages of π-JJs in adiabatic quantum-flux-parametron (AQFP) logic, which is an adiabatic superconductor logic based on the quantum-flux-parametron. First, we show that AQFP logic with π-JJs (π-AQFP) can operate using only π-JJs and can be powered and clocked in the same way as the conventional AQFP logic. Then, we show that π-AQFP logic can realize inverters without using signal transformers, which generally occupy a large area in AQFP gates and are difficult to miniaturize. We demonstrate π-AQFP inverters using numerical simulation to establish that π-AQFP logic operates adiabatically and robustly. Our results show that π-JJs can be easily incorporated into AQFP logic and enhance the circuit density of AQFP logic.
The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low-temperature 4 kA/cm 2 , 1.75-μm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in 2001 are currently under testing at TRW.