We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy.
We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy.
We present an adiabatic microprocessor based on Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4b data words. We demonstrate register file R/W access, ALU execution, and program branching performed at 100kHz under the cryogenic temperature of 4.2K. We also successfully demonstrated a high-speed chip of the microprocessor execution units up to 2.5GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP) which has a switching energy of 1.4zJ when driven by a 4-phase 5GHz ac-clock at 4.2K.
Abstract We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.
We report recent progress on adiabatic quantum-flux-parametron (AQFP) logic, which is an energy-efficient superconductor logic based on quantum flux parametron (QFP). The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching, in which the shape of the potential energy gradually varies between single-well and double-well shapes as the result of using ac excitation magnetic fluxes. First, we show the operation principle of AQFP and explain adiabatic switching in light of potential energy shapes. We also show calculated switching energy and bit error rates to demonstrate that the switching energy of AQFP can be significantly reduced while keeping a low error rate. Then, we report recently developed AQFP subsystems, which include an 8-bit carry look-ahead adder, a register file, and a long-interconnect driver. Our demonstration reveals that AQFP technology is ready to be applied in microprocessor design.
Complementary metal-oxide-semiconductor (CMOS) circuit technology has sustainedthe exponential growth of computing power for more than 20 years. However, it hasbeen estimated that the power consumption of a next-generation supercomputer willexceed the power supplied from a single power plant. This indicates the need to dramaticallyimprove the energy efficiency of logic devices to achieve future high-endcomputers.As an extremely energy-efficient logic, we proposed and have been investigatingadiabatic quantum-flux-parametron (AQFP) devices. Due to adiabatic switching operations,its bit energy (energy dissipation per bit) can go below Ic 0, where Ic is acritical current of a Josephson junction and 0 is a single-flux-quantum (SFQ). Ic 0corresponds to the energy dissipated at every 2 phase transition in conventional nonadiabaticsuperconductor logics.We have two objectives in this study. One is to reveal physical energy bounds oncomputation through investigation of the energy efficiency of AQFP logic. The otheris to develop fundamental circuits necessary for energy-efficient computing systemsusing AQFP logic.First, we numerically and experimentally demonstrated the sub-Ic 0 bit-energyoperations of AQFP gates to show that AQFP gates operate in adiabatic modes. Weinvestigated the dependence of energy dissipation and operation margins on circuitparameters. After optimizing the parameters, we calculated the bit energy and the biterror rate at 4.2 K to verify the sub-Ic 0 bit-energy operations at a finite temperature.Additionally, we measured the bit energy of an AQFP gate using a superconductorresonator-based method.Secondly, we numerically demonstrated the sub-kBT bit-energy operations, wherekB is the Boltzmann constant and T is temperature, to show that AQFP gates can operatebeyond thermodynamic energy bounds. We investigated the dependence of energydissipation on operation frequencies and damping conditions of Josephson junctions.By using underdamped junctions, we confirmed the sub-kBT bit-energy operationsat a finite temperature thorough circuit simulation. This result indicates that thereis no minimum energy dissipation required for the operations of AQFP gates unlessthe entropy of the system decreases, which corresponds to the Landauer’s argument on the minimum energy dissipation for computation. Also, we discussed quantummechanicalenergy bounds and experimentally demonstrated AQFP gates with underdampedjunctions.Additionally, we investigated reversible computing using AQFP logic with underdampedjunctions, in order to deal with an important but unresolved question: “Isreversible computing achievable by using practical devices?” We built a purely reversiblegate by using AQFP gates, which we designated as the reversible quantumflux-parametron (RQFP) gate. We calculated its energy dissipation and confirmed thatthere is no minimum energy dissipation for reversible logic operations using RQFPgates. To the best of our knowledge, these are the first calculation results that show nominimum energy dissipation in reversible computing that use practical circuit structures.Moreover, our experimental results have demonstrated the logical and physicalreversibility of the RQFP gate. We believe that this is the first demonstration thatshows both logical and physical reversibility using practical devices.Finally, we proposed a novel energy-efficient latch for AQFP logic, which we designatedas the quantum-flux-latch (QFL). Latches are necessary circuitries in largecomputing systems but had been missing in AQFP logic. We discussed its energyefficiency through simulation and experimentally demonstrated correct operations ofthe QFL and a 1-bit shift register using QFLs. Also, we proposed high-speed test circuitsusing QFLs and experimentally demonstrated logic operations of AQFP circuitsat high speed.We strongly believe that our results showed the extremely high energy efficiency ofAQFP logic. These results will move the AQFP logic to practical usage as extremelyenergy-efficient integrated circuits.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority,and, andorfunctions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.