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International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)

Adder Circuit on IBM Universal Quantum Computers

Wiphoo Methachawalit, Prabhas Chongstitvatana

Published Jun 1, 2020• 5 citations
Publisher

Abstract

This paper reports the experiments on IBM quantum devices. We design an adder circuit based on Thomas G. Draper proposal. This circuit is a part of a general circuit to build Shor prime number factorization algorithm. We perform the experiments on three IBM quantum devices. The result of the experiment shows that on IBM Essex device, the best possible adder for one qubits has 100% accuracy. However, the results for two qubits adder circuit are much worse. The details analysis of the accuracy of three IBM devices are reported.

DOI
10.1109/ecti-con49241.2020.9158064

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This paper reports the experiments on IBM quantum devices. We design an adder circuit based on Thomas G. Draper proposal. This circuit is a part of a general circuit to build Shor prime number factorization algorithm. We perform the experiments on three IBM quantum devices. The result of the experiment shows that on IBM Essex device, the best possible adder for one qubits has 100% accuracy. However, the results for two qubits adder circuit are much worse. The details analysis of the accuracy of three IBM devices are reported.
Quantum Fourier Transform (QFT) is an essential algorithm for quantum computers. There are many uses of QFT in the application of quantum computing. In this work, we proposed a generalized adder circuit that was fundamental for QFT. We designed and ran the experiments with the proposed adder circuit on an IBM quantum computer facility. We observed that the number of qubits was one factor in the error rate. We found that our proposed two-qubits adder circuit running on the IBM quantum computer had an error rate of around 25%. The complexity of the adder circuit includes qubit connectivity, physical devices, and error from noise due to the environment. We demonstrated the constraints of the proposed adder circuit.
Quantum computing has gained a lot of interest recently because of its claims of solving some problems that are almost impossible solving in classical computing.Prime factorization of big numbers using Shor's algorithm and Grover database search algorithm are two of them.Furthermore, quantum algorithms are developed to make it more realistic in real world.In classical computing the basic unit of computation is a bit which is in 0 or 1 state at a time, whereas in quantum computing it is called a qbit which can be 0 and 1 at the same time and we call it superposition.This paper proposes an implementation of quantum full adder using IBM quantum experience.Quantum circuits are drawn using Qiskit and run on Qiskit simulators, IBM quantum simulators and real IBM quantum machines.Proposed circuit will help in future for drawing more complex circuits and algorithms.
Quantum computers are able to efficiently solve certain problems that are very computationally demanding or even intractable on classical computers. With recent advances in quantum computing hardware, we are entering an exciting era where it is becoming possible to execute ‘useful’ quantum algorithms. However, quantum computers will continue to be noisy for the foreseeable future. In this paper, quantum adder circuits are used to evaluate three simple error mitigation methods: (1) error correction through the use of replicated circuits and a voter circuit, (2) error detection by encoding, which involves expanding the qubit space and partitioning it into orthogonal subspaces consisting of correct and incorrect code words, and (3) error mitigation by reducing circuit depth at the expense of increasing the number of qubits. These three mitigation methods are what we dub replication, encoding, and simplification, respectively. We find simplification to be most effective for implementing the simple quantum adders on the IBM Quantum Experience, while replication increases the gate count and the error count on current quantum devices. The encoding methods used in this study proved to be not effective for even the simple adder circuits that were implemented, suggesting the need to study and evaluate more sophisticated error correcting schemes.
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
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One of the critical limitations quantum computers are yet to overcome is quantum errors. Efforts have been made in quantum error correction fields to overcome them. However, since we are bound by the technology of this noisy intermediate-scale quantum era, it is important that we focus on the efficiency and optimization of our error correction circuits. In this paper, we present a way of extending quantum error correction circuits using quantum adders by utilizing the notion of majority voting over all the qubits. We use adder circuits and a comparator to achieve majority voting. We demonstrate how our proposed methodology exhibits a linear trend in the required number of quantum gates. Further, we confirm the accuracy and efficacy of our proposed methodology for optimizing the number of quantum gates through extensive simulation in IBM's Qiskit and compare them with existing literature.