Complex computing environment is switching from peta scale to exa scale. Conventional irreversible logic will not be going to sustain forever and power dissipation need to be controlled. Lot of research is going on to avoid power dissipation due to switching but only a few research efforts have been applied on power dissipation due to loss of bits. Reversible computing is found to be one of the emerging and promising technologies to overcome addressed power dissipation due to loss of bits. Quantum cost is one of important metric of comparison and required further for analyzing performance of one reversible logic based circuit over other. This paper proposes the algorithm to draw optimized quantum implementation of reversible logic gates and further utilized for investigation of quantum cost. The optimized quantum cost obtained from proposed method is verified using RCViewer+ tool.
Complex computing environment is switching from peta scale to exa scale. Conventional irreversible logic will not be going to sustain forever and power dissipation need to be controlled. Lot of research is going on to avoid power dissipation due to switching but only a few research efforts have been applied on power dissipation due to loss of bits. Reversible computing is found to be one of the emerging and promising technologies to overcome addressed power dissipation due to loss of bits. Quantum cost is one of important metric of comparison and required further for analyzing performance of one reversible logic based circuit over other. This paper proposes the algorithm to draw optimized quantum implementation of reversible logic gates and further utilized for investigation of quantum cost. The optimized quantum cost obtained from proposed method is verified using RCViewer+ tool.
Increasing miniaturization and demand of low power electronics is highly motivating research on reversible logic. Reversible logic has attracted signification attention in fields of Low power VLSI design, computer graphics, quantum computing and communication. A lot of work has been done on synthesis and optimization of reversible circuits followed by quantitative analysis on various optimization metrics like ancillary inputs, garbage outputs and quantum cost. It is therefore obvious to present a quick guide on reversible logic implementation to bridge gap between theory and implementation. Taxonomy diagrams of work done in reversible logic domain are also presented to give a quick review of all about reversible logic. Quantum realization of popular reversible Fredkin gates using RCViewer tool is also presented which will be stepping stone for a new researcher to synthesize and optimize any complex reversible logic based circuit.
Energy dissipation is the important constrain in the design and implementation of VLSI circuits. Usage of Reversible logic circuit is the best solution for lower energy dissipation. In this paper, basic reversible gates and some existing gates and KMD gates are realized using the Quantum Equivalent structure and the Controlled-V and V+ gate structure from their functional expression. Using the qubit gate reduction procedure of quantum circuit, the quantum cost and number of primitive gates of the functional expression are deduced. After synthesizing the Quantum Cost (QC), Gate count (GC), Garbage Output (GO), number of gates, constant inputs are compared with the non-optimized circuit. The quantum circuit and controlled V and V+ structure are realized in RCViewer+ tool using .tfc (“Toffoli-Fredkin Cascade”) code.
Nowadays, reversible computing is more fascinative research area to curtail power dissipation in comparison of conventional computing. In conventional computing, logic circuit dissipates more power by losing bits of information. Reversible computing recovers from losing bits of information through same number of output vector from same number of input vector and thus decreases the power dissipation. Since there are different cost considerations such as garbage outputs, gate count, quantum cost methods for specific cost reductions may be established.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Quantum is an emerging technology in future computers. Reversibility is the main advantage of quantum computers. In conventional computers, the computation is irreversible i.e. the input bits are lost once the logic block generates the output and input bits cannot be restored but it can be done in reversible computation because in reversible computation the inputs and outputs have a one-to-one correspondence. Therefore, a reversible gate input could even be uniquely determined from their output which leads to less power consumption. Hence the complexity of the digital circuits can be reduced by using reversible computing. In quantum computer to perform reversible operations, we need to implement the reversible gates using quantum gates. In this paper, we discussed various reversible logic gates like Feynman, Toffoli, R, Peres and TR gates using basic quantum gates like CNOT, Pauli, Swap gates and their implementation using IBM quantum experience.
One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.