Progress towards innovative and energy efficient logic circuits
S. Pagano, G. Salina, Anna Napoli, C. Attanasio, C. Barone, F. Bobba, Giovanni Carapella, Antonio Leo, A. Nigro, Roberto Cristiano, Mikkel Ejrnaes, Mikhail Lisitskiy, Nadia Martucciello, Giovanni Piero Pepe, L. Parlato, Matteo Cirillo, M. Lucci, Vittorio Merlo, ANTONINO MESSINA, Benedetto Militello
Abstract The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported
Abstract The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported
Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10[superscript -19] J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm ×7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
Superconducting nanowire integrated circuits (SNICs) are a promising class of cryogenic electronics that harness the zero resistance, high kinetic inductance, and nanoscale geometry of ultrathin superconducting wires to implement logic, memory, amplification, and sensing with minimal energy dissipation. Unlike Josephson-junction-based circuits, SNICs support compact, planar layouts compatible with single-layer fabrication and operation in unshielded cryogenic environments. This thesis develops superconducting nanowire memory (SNM) as a scalable implementation of SNICs. A modular cell architecture is introduced, exploiting hysteretic switching and inductive asymmetry to enable nonvolatile digital state storage with zero static power consumption. A hierarchical design framework is established, combining automated layout generation, electrothermal simulation in LTspice, and microscopic modeling using the time-dependent Ginzburg–Landau (TDGL) formalism. To enable scalable integration, this work implements a row–column SNM array layout and demonstrates fabrication across full 4-inch wafers using a planar, singlelayer process. Cryogenic measurements validate reliable operation in both single cells and multi-cell arrays, confirming the predictive accuracy of the design and modeling framework. Tradeoffs in bias current levels, pulse timing, and read/write conditions are systematically evaluated through cryogenic measurements, revealing their impact on bit error rate, operational margins, and energy efficiency across single cells and arrays. Together, these contributions establish SNICs as a viable and extensible platform for cryogenic memory, providing the tools, models, and infrastructure needed to enable broader adoption in quantum computing, neuromorphic systems, and other energy-constrained cryogenic applications.
The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.
Superconducting nanowire logic device is a new type of the cryogenic digital logic device. It has a series of characteristics such as fast speed, low power consumption, high gain, stable driving ability and simple fabrication process. It can be used to design superconducting digital circuits. In this paper, The ‘and/or’ basic logic gate structure is designed based on superconducting nanowires and a fabrication scheme of the device is developed based on micro-processing equipment. After building the system test circuit, the function of the ‘and’ gate and ‘or’ gate operating at 10 MHz frequency is verified.
Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.