13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with $4.6\mu\mathrm{V}$ Precision and $4.1 \text{nV}/\text{Hz}^{0.5}$ Noise Co-Integrated with the Single Electron Transistor at 60mK
Yingjie Li, Yifei Zhang, Haichuan Lin +1 more
Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around$10\mu \mathrm{V}$. Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6].
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference•Feb 16, 2025•7 citations