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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with $4.6\mu\mathrm{V}$ Precision and $4.1 \text{nV}/\text{Hz}^{0.5}$ Noise Co-Integrated with the Single Electron Transistor at 60mK

Yingjie Li, Yifei Zhang, Haichuan Lin, Cheng Wang

Published Feb 16, 2025• 7 citations
Publisher

Abstract

Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around$10\mu \mathrm{V}$. Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6].

DOI
10.1109/isscc49661.2025.10904579

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13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV4.6\mu\mathrm{V}4.6μV Precision and 4.1nV/Hz0.54.1 \text{nV}/\text{Hz}^{0.5}4.1nV/Hz0.5 Noise Co-Integrated with the Single Electron Transistor at 60mK
Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around10μV10\mu \mathrm{V}10μV. Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6].
Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a μ\muμ-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.
A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction. With each physical qubit needing multiple control lines however, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired-up via miniaturized interconnects. Even so, heat and crosstalk from closely integrated control have potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise. Here, we benchmark silicon MOS-style electron spin qubits controlled via heterogeneously-integrated cryo-CMOS circuits with a low enough power density to enable scale-up. Demonstrating that cryo-CMOS can efficiently enable universal logic operations for spin qubits, we go on to show that mill-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our milli-kelvin CMOS platform, with some 100-thousand transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a chiplet style control architecture.
Abstract A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction1–3. However, with each physical qubit needing multiple control lines, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware4–6. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired up by miniaturized interconnects7–10. Even so, heat and crosstalk from closely integrated control have the potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise11,12. Here we benchmark silicon metal-oxide-semiconductor (MOS)-style electron spin qubits controlled by heterogeneously integrated cryo-complementary metal-oxide-semiconductor (cryo-CMOS) circuits with a power density sufficiently low to enable scale-up. Demonstrating that cryo-CMOS can efficiently perform universal logic operations for spin qubits, we go on to show that milli-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our sub-kelvin CMOS platform, with about 100,000 transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a ‘chiplet-style’ control architecture.
The understanding of quantum mechanics enabled the development of technology such as transistors and has been the foundation of today’s information age. Actively using quantum mechanics to build quantum technology may cause a second revolution in handling information. However, to execute meaningful algorithms, largescale quantum computers have to be built. Such systems are constructed from many qubits, the quantum version of the classical bit. While exciting progress is being made across a range of different qubit platforms, achieving the radical scalability that is necessary to build a largescale processor could be a roadblock. Huge challenges are put on reproducibility, inand output connectivity and material quality. Qubits based on the spins of electrons and holes confined in semiconductor quantum dots may have an important advantage in constructing quantum processors. This platform can profit from the advanced semiconductor industry that was responsible for the first computing revolution. Group IV semiconductors such as silicon and germanium have a high compatibility with industrial semiconductor manufacturing and contain stable isotopes with zero nuclear spin. The materials can be isotopically purified and serve as excellent hosts for spins with long quantum coherence. In Chapter 3 we present quantum dot arrays in silicon metaloxidesemiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/SiGe). A nearly identical integration scheme based on an overlapping gate structure can be used to define quantum dots in each platform. Each platform has its own opportunities, which are carefully assessed. By employing charge sensing we confirm that all quantum dots can be depleted to the singleelectron regime. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. Using this crossplatform integration, we can study qubits in each platform with minimal overhead. Long coherence times, excellent singlequbit gate fidelities and twoqubit logic have been demonstrated with SiMOS spin qubits, making it one of the leading platforms for quantum information processing. However, due to the high disorder at the Si/SiO2 interface compared to Ge/SiGe and Si/SiGe interface, quantum dots defined in SiMOS are small and achieving sufficient control over single electrons has been a long standing challenge. In Chapter 5 we show experiments on a double quantum dot that can be isolated from its reservoir. We demonstrate a tunable tunnel coupling between single electrons up to 13 GHz and tunable tunnel rates down to below 1 Hz. These results mark an important step towards the required degree of control over the location of and coupling between quantum dots, necessary for the operation of a large array.
The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of DC bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this paper presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryo-CMOS demultiplexer and a cryo-CMOS DC DAC have been developed in a 22-nm FinFET process to control a co-developed 2D-array designed with 648 Single Hole Transistors (SHTs). Thanks to the dissipation below 120μ\muμW, the whole system operates at temperatures below 70mK in a custom-built electrical/mechanical infrastructure embedded in a standard singlepulse- tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold (S/H) structures, allowing to store 96 unique bias voltages over a 3V range with a voltage drift between 60μ\muμV/s and 18 mV/s. This work demonstrates a tight integration at mK-temperatures of cryo- CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors towards the large number of qubits required for a practical quantum computer.
While large-scale fault-tolerant quantum computers promise to enable the solution to certain classes of problems for which no other efficient approach is known, such a machine is believed to require over a million performant qubits. Scaling today's 0(100) qubit superconducting (SC) quantum computers to this extent while also improving performance carries many daunting challenges, including control of such a large quantum processor (QP). Integrating the control electronics at an intermediate temperature stage within the cryostat is an attractive option, e.g., due to the inherent thermal stability of the cryogenic environment and the feasibility of connecting to the QP via dense low-loss/high-thermal-isolation SC lines [1], [2]. Several cryo-CMOS quantum controllers have been reported, with examples used to control spin [3] and transmon [1], [2] qubits. To date, IC-based quantum control experiments have focused on resonant RF control, but baseband signals are often central to the execution of gates. Here, we report the design and system characterization of a cryo-CMOS IC for generating both the RF and baseband signals required for full control of a SC QP unit-cell, and show its ability to implement the components of a high-fidelity gate set that is universal for quantum computing.