In this paper we propose a simulation system for LDPC codes implemented on a field-programmable gate array device. The presented system includes an LDPC encoder, Gaussian noise generator and an LDPC decoder. An LDPC encoder and decoder are fully flexible and support different constructions of LDPC codes. It makes possible to obtain performance curves of a large number of LDPC codes and analyse their properties. We have found that the LDPC code proposed in [1] has an error floor higher than the LDPC code proposed by the experimental specification CCSDS 231.1-O-l. We have evaluated the performance of 2250 (128,256) LDPC codes with our simulation system and have found an LDPC code that outperforms the LDPC code from the experimental specification CCSDS 231.1-O-l.
In this paper we propose a simulation system for LDPC codes implemented on a field-programmable gate array device. The presented system includes an LDPC encoder, Gaussian noise generator and an LDPC decoder. An LDPC encoder and decoder are fully flexible and support different constructions of LDPC codes. It makes possible to obtain performance curves of a large number of LDPC codes and analyse their properties. We have found that the LDPC code proposed in [1] has an error floor higher than the LDPC code proposed by the experimental specification CCSDS 231.1-O-l. We have evaluated the performance of 2250 (128,256) LDPC codes with our simulation system and have found an LDPC code that outperforms the LDPC code from the experimental specification CCSDS 231.1-O-l.
In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.
Low-density parity check (LDPC) codes with their near-Shannon capacity limit error correcting performance and iterative decoding algorithm are being evaluated for digital communications applications. For LDPC codes to be used in real systems, their error floors need to be investigated. In this paper, we evaluate the performance of disjoint difference set (DDS)-based LDPC codes (with column weights 3, 4, 5) and array code-based LDPC codes (with column weights 3, 4, 5) in the additive white Gaussian noise (AWGN) channel using a high-speed field programmable gate array (FPGA) simulation platform. The error floor regions (bit error rates down to 10/sup -12/) of those codes are presented. For better performance of array codes, a girth optimization method is proposed and the FPGA evaluation results are presented.
With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this paper, a 9-k code length multi-rate LDPC decoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 code mode, the regular 5/8 code mode, and the regular 7/8 code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10/sup -7/ at signal-to-noise ratio of 1.8 dB.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. In many digital communication systems these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. In this research work finite fields construction method is used and diverse techniques like masking, dispersion and array dispersion for the construction of parity check matrix H. These constructed codes are then simulated to make the performance evaluation. The key interest of this research work was to inspect the performance of LDPC codes based on finite fields. A comprehensive masking technique was also an objective of this research work. Simulation was done for different rates using additive white Gaussian noise (AWGN) channel. In MATLAB a library of different functions was created to perform the task for base matrix construction, dispersion, masking, generator matrix construction etc. Results give an idea that even at BER of 10-6 these short length LDPC codes performed much better and have no error floor. BER curves are also with 2-3dB from Shannon’s limit at BER of 10-6 for different rates.
Future technologies such as cognitive radio require flexible and reliable hardware architectures that can be easily configured and adapted to varying coding parameters.The objective of this work is to develop a flexible hardware encoder and decoder for low-density parity-check (LDPC) codes.The design methodologies used for the implementation of a LDPC encoder and decoder are flexible in terms of parity-check matrix, code rate and code length.All these designs are implemented on a programmable chip and tested.Encoder implementations of LDPC codes are optimized for area due to their high complexity.Such designs usually have relatively low data rate.Two new encoder designs are developed that achieve much higher data rates of up to 844 Mbps while requiring more area for implementation.Using structured LDPC codes decreases the encoding complexity and provides design flexibility.The architecture for an encoder is presented that adheres to the structured LDPC codes defined in the IEEE 802.16e standard.A single encoder design is also developed that accommodates different code lengths and code rates and does not require re-synthesis of the design in order to change the encoding parameters.The flexible encoder design for structured LDPC codes is also implemented on a custom chip.The maximum coded data rate of the structured encoder is up to 844 Mbps and for a given code rate its value is independent of the code length.An LDPC decoder is designed and its design methodology is generic.It is applicable to both structured and any randomly generated LDPC codes.The coded data rate of the decoder increases with the increase in the code length.The number of decoding iterations used for the decoding process plays an important role in determining the decoder performance and latency.This design validates the estimated codeword after every iteration and stops the decoding process when the correct codeword is estimated which saves power consumption.For a given paritycheck matrix and signal-to-noise ratio, a procedure to find an optimum value of the maximum number of decoding iterations is presented that considers the affects of power, delay, and error performance.