A Investigation of a New Superconducting Logic Family: Design and Experimental Low-Speed Testing of its Circuits

S. Pagano, G. Salina, Anna Napoli +17 more

Abstract The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported

Howard Cam Luong, T. Van Duzer

J. Fleischman

This dissertation presents the design, fabrication, and testing of a flux-shuttle shift register and a discussion of computer architecture and systems for various superconducting digital logic families. While superconductive digital logic provides very fast switching speed (a few picoseconds), it is necessary to carefully consider the application and the computer architecture being used to implement a digital system when designing for maximum performance. The first part of this dissertation addresses architecture issues. First, a brief description of superconducting digital logic fundamentals is provided. The basic concepts of various techniques used in current high-performance computing systems are then presented. Since system architecture is greatly influenced by the characteristics of the logic family used, we then describe three superconducting logic types in detail. The characteristics of each of these logic families are examined, and their influence on architecture is discussed. The system requirements of general-purpose computing and digital signal processing are investigated. Due to the demands placed on random access memory by general-purpose computing, we conclude that the most practical digital system currently realizable in superconducting technology is based on digital signal processing (DSP). Finally, three example DSP systems are explored. Part II of this dissertation concentrates on the design, fabrication, and testing of a shift register, an important part of many DSP systems. Several shift registers using different logic types are evaluated. The design and testing of a flux-shuttle shift register using direct injection clocks are presented. The circuit was experimentally verified to work with wide operating margins at low speed. While simulations indicate that the shift register will operate at more than 60 GHz, high-speed test of the shift register was limited to 1 GHz by available test equipment.

T. Van Duzer

Massoud Pedram, Yanzhi Wang

Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.

Mutuso Hidaka