Quantum Computing is an emerging field of technology with the promise that engineered quantum systems can address hard problems such as, problems with exponential compute complexity in Chemistry, Genomics, Optimization and many more applications. Quantum Computer Architecture is an area of research targeted for the NISQ-era quantum computing and little research has been done for development of a scalable classical control and read-out infrastructure for the quantum processors. The project is aimed at study of SoC-FPGA design methodology and architecture design for control of quantum processor. The targeted quantum hardware is the Spin-Qubit in Semiconductor Quantum Dot Chip. The project is intended for understanding the design and working of a silicon-spin qubit for a computer (architecture) engineer. It further helps identify necessities for an architecture, Instruction Set requirements, bottlenecks and future challenges (specific to Spin-Qubit quantum processor) that would help in better designs for new control architectures. The objective of this thesis is directed towards addressing the architectural challenges for the quantum-classical hardware for controlling the NISQ-era quantum devices and beyond. We analyze the control infrastructure requirements and propose a micro-architecture and waveform generation methodology to integrate the physical device with the quantum compilation tool-chain.
Quantum Computing is an emerging field of technology with the promise that engineered quantum systems can address hard problems such as, problems with exponential compute complexity in Chemistry, Genomics, Optimization and many more applications. Quantum Computer Architecture is an area of research targeted for the NISQ-era quantum computing and little research has been done for development of a scalable classical control and read-out infrastructure for the quantum processors. The project is aimed at study of SoC-FPGA design methodology and architecture design for control of quantum processor. The targeted quantum hardware is the Spin-Qubit in Semiconductor Quantum Dot Chip. The project is intended for understanding the design and working of a silicon-spin qubit for a computer (architecture) engineer. It further helps identify necessities for an architecture, Instruction Set requirements, bottlenecks and future challenges (specific to Spin-Qubit quantum processor) that would help in better designs for new control architectures. The objective of this thesis is directed towards addressing the architectural challenges for the quantum-classical hardware for controlling the NISQ-era quantum devices and beyond. We analyze the control infrastructure requirements and propose a micro-architecture and waveform generation methodology to integrate the physical device with the quantum compilation tool-chain.
Building a quantum computer is not only about having qubits or quantum processors, analogously to classical computers are not only based on transistors or integrated circuits. Accordingly, in the very recent times, a few unique research groups in academia and companies have been exploring and proposing high-level and low-level programming languages, compilers, microarchitecture and instruction set architectures for quantum computation as well as different computer architecture approaches. In other words, developing a quantum computer requires bridging quantum applications and quantum devices. This talk will address the main challenges of building a scalable full-stack quantum computing system followed by a discussion on its architecture focusing on fault tolerance and compilation of quantum algorithms on NISQ devices. I will also provide my vision on how the research community could accelerate the process towards building such a scalable quantum machine, potentially through vertical cross-layer co-design structured methodologies.
Quantum computing has made significant strides, with hardware platforms now advanced enough to tackle the challenges of scaling up to larger and more robust systems. Central to this progression is the interface between quantum processors, comprising isolated qubits, and the classical systems required for their control and readout. As these systems transition from few-qubit devices to fault-tolerant architectures, the complexity of this quantum-classical interaction poses significant engineering challenges. Field-Programmable Gate Arrays (FPGAs) have emerged as an adaptable and efficient solution, offering realtime control, low-latency operations, and seamless integration. This review delves into current FPGA-based platforms, including commercial systems, as well as open-source solutions developed by academic research groups. The architecture, features, and contributions of these platforms to addressing scalability and integration issues are thoroughly examined. Additionally, the review highlights innovations in cryogeniccompatible controllers and explores the potential of Cryo-FPGAs to reduce noise and improve fidelity in quantum systems. By providing a comprehensive analysis of current technologies and identifying opportunities for advancement, this review offers valuable insights for researchers and engineers working to develop scalable quantum computing solutions.
Silicon-based spin qubits have emerged as a promising platform for scalable quantum computation due to their compatibility with advanced semiconductor fabrication and integration with classical CMOS electronics. As fabrication capabilities advance toward larger, higher-yield devices, the field is transitioning from academic prototypes toward processors ultimately requiring millions of qubits. This shift places increasing emphasis on developing operating techniques that scale with qubit number. In this thesis, a four qubit SiMOS processor is used to investigate three key aspects of multi-qubit operation for spin-based quantum computing. First, tuning and operation techniques for parallel double-quantum-dot unit cells are developed. Electron loading strategies enable four-qubit operation in an isolated charge configuration, and universal single- and two-qubit control is demonstrated. The native gate set is characterised using gate set tomography. The processor is operated as two unit cells that can be initialised and read out in parallel, providing two independent parity measurements per shot, without increasing operation time or degrading state preparation and measurement fidelity. Second, control techniques for generating multi-qubit entangled states and executing general quantum circuits are established. Three-qubit maximally entangled states, including cluster and Greenberger–Horne–Zeilinger states, are generated and measured with a maximum fidelity of 82.5%. A Mermin value of 3.14 is achieved, certifying genuine tripartite entanglement. A fully symmetric dynamically decoupled gate sequence is developed, extending the entanglement lifetime beyond T2* to a limit set by T2-Hahn. A workflow for compiling, executing, and analysing arbitrary circuits from OpenQASM is also demonstrated. Finally, the first mid-circuit measurements in a silicon spin-qubit system are presented. This capability is extended to feedforward control, including a novel “in-layer” method that performs conditional phase operations without routing information to the classical control layer. This approach leverages measurement-induced backaction as a control mechanism. Both in-layer and FPGA-enabled feedforward strategies are benchmarked, and their dominant error channels are identified.
Modern society increasingly depends on ever more capable computing devices. Yet some important problems remain beyond the reach of classical computers due to their inherent computational complexity. At the same time, the energy required to power this growing computational demand is an important concern. Over the past decade, quantum computers have received increased attention, not as a replacement for classical systems, but as a complementary technology with the potential to tackle complex problems more efficiently and significantly boost computational performance. This is made possible by leveraging the principles of quantum mechanics. To achieve this, quantum computers rely on a fundamental basic block called a qubit. There are several different technologies for realizing qubits, and no single approach has yet established itself as the definitive choice. In this work, we focus on silicon spin qubits in quantum dots, which use the intrinsic spin states of an electron as the computational basis states. This platform offers notable advantages including long coherence times, compatibility with the existing semiconductor industry and scalability. However, this technology is still very immature and substantial progress is still required. Just like for the design of classical electronics, simulations can play a crucial role by reducing development cycles, lowering costs, and improving overall efficiency. Throughout this thesis, we will propose a comprehensive simulation framework that allows to study and design spin qubit systems focusing on key aspects of the system architecture. First, a spin qubit compact model is presented that enables the co-simulation of spin qubits together with the classical CMOS control and readout circuitry that will significantly impact the performance of the qubits. We show that the model is capable of including all elements to build an elementary quantum gate set and illustrate its use by co-simulating a spin qubit coupled to a readout resonator with a complete cryo-CMOS readout chip design in a commercial electronic design automation tool. Next, we discuss a hybrid-Hamiltonian simulation approach that is aimed at simulating spin qubit microarchitectures that are suited for running quantum error correction protocols, which protect the encoded information against the errors that unavoidably happen due to the inherently noisy physical qubit devices. This simulation approach incorporates several novel strategies to tackle the challenge of the required computing power that grows exponentially with the size of the simulated system. Furthermore, additional functionality is incorporated to evaluate and track the performance of the implemented error correction protocols. Finally, we propose a characterization protocol for constructing a correlated noise model of the charge noise that is an important factor affecting spin qubit performance. The sources of charge noise are modelled as two-level fluctuators and the entire qubit array is characterized by dividing it into patches and running batches of benchmarking quantum gate sequences. The resulting noise model enables to scale the simulations to larger system sizes and to study the system performance and hardware demands of error correction protocols. Together, these models form a multi-layer simulation framework that enables detailed analysis and optimization of future spin qubit microarchitectures, with particular emphasis on error correction protocols. As such, the framework contributes to the realization of practical large-scale quantum computing.
Despite Noisy Intermediate-Scale Quantum devices being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed to enable successful algorithm executions. Not so much attention has been paid to mapping and compilation implementations for spin-qubit quantum processors due to the scarce availability of experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring solutions on such devices. In this work, we discuss the unique mapping challenges of a scalable crossbar architecture with shared control and introduce SpinQ , the first native compilation framework for scalable spin-qubit architectures. At the core of SpinQ is the Integrated Strategy that addresses the unique operational constraints of the crossbar while considering compilation scalability and obtaining a O(n) computational complexity. To evaluate the performance of SpinQ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping techniques that could increase algorithm success rates on this architecture and potentially inspire further research on quantum circuit mapping for other scalable spin-qubit architectures.
Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.