Design of a high speed Josephson shift register

강광용, 강준희, 서정대 +9 more

Huang-Tian Chan

John X. Przybysz

A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al/sub 2/O/sub 3//Nb technology. Junctions with critical current densities near 10 kA/cm/sup 2/ would make 100-GHz shift registers feasible.>

V. Nandakumar, T. Van Duzer

The design of a very-high-speed Josephson junction shift register is presented. Computer simulations show that the circuit can be operated with a two-phase sinusoidal clock at frequencies over 60 GHz. The shift register is based on using nonlatching superconducting interferometric switches to shift a bias current between arms of superconducting loops. The operating margins of the circuit are discussed.>

S. Hasuo

Oleg A. Mukhanov

The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>