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High-Performance and Energy-Efficient Decoder Design for Non-Binary LDPC Codes

Yuta Toriyama

Published Jan 1, 2016• 0 citations
OpenAlex

Abstract

Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts.Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency.We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)•Nov 28, 2021•1 citation
Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts.Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency.We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.
Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.
Compared to binary Low-Density Parity-Check (LDPC) codes, nonbinary LDPC (NB-LDPC) codes have better error correction performance under short-to-moderate block lengths or high-order modulations. Traditional min-sum-based soft decoding algorithms for NB-LDPC codes suffer from large computational complexity, which leads to inefficient hardware implementations. The Multiple-symbol-reliability weighted Bit-Reliability-Based (MwBRB) hard decoding algorithm achieves a good tradeoff between error correction performance and decoding complexity. However, efficient hardware implementations based on the MwBRB algorithm have not been investigated. In this brief, an improved layered MwBRB algorithm is first proposed, which results in faster convergence rate than the MwBRB algorithm. Then, an ultra-high-throughput low-complexity decoder architecture with an efficient partially parallel processing schedule is also presented. Finally, the proposed architecture is coded with RTL and synthesized under the TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed decoder for a (837, 726) quasi-cyclic NB-LDPC code over GF(25) achieves a throughput of 21.66 Gbps and an area efficiency of 4.77 Gbps/M-gates under the TSMC 90-nm CMOS technology. The proposed decoder reaches a throughput more than 20 Gbps for the first time among the prior NB-LDPC decoders, and the area efficiency is far beyond the state-of-the-art designs.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward-backward, syndrome-based, and pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This paper is specially impacting check nodes of high degrees (or high coding rates). Results of 28-nm ASIC post-synthesis for a check node of degree 12 (i.e., a code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared with the classical forward-backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256), and these preliminary results open the road to high decoding throughput, high rate, and high-order Galois field NB-LDPC decoder with a reasonable hardware complexity.
This paper proposes an iterative Non-Binary LDPC (NB-LDPC) decoder for non-binary codes constructed using the 5G base matrices. Motivated by the binary to non-binary replacement method, we construct NB-LDPC matrices devised directly from the 5G base matrices. Subsequently, we develop an iterative decoding scheme able to facilitate parallelism due to its low complexity and to offer high performance due to its fast convergence. BER plots comparing Min-sum binary decoder (over 5G base matrices) to our proposed NB decoder reveal a performance gain of 0.5 dB in certain cases. Furthermore, hardware synthesis results obtained for a 45-nm ASIC technology are provided in order to quantify the throughput rate and area requirements of the proposed architecture. It is shown that the proposed decoding architecture, because of its independence on the lifting size factor, can offer higher throughput rate than the binary ones for small codeword lengths and code rates. In addition, as Galois Field (GF) order increases, the throughput rate increases too. Finally, the throughput-to-area show that the proposed NB architecture is generally suitable for small lifting size factors.